From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F09FD3E6DFA for ; Fri, 10 Jul 2026 21:55:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783720513; cv=none; b=J7H7HL23whYBy1mRWIRy2jkoN1wFtIO+0zdyPy6kwPDLekACn+W3yp12TopArlvRpOcH1+YJ7FYi1jTUqOVmGg88dHZ6y6iJxoByfYqpTVoHE0bwEeUV1msQuzYuimlL84yuyrODkU3lDZmllMOtRE3O/zKgJ3efhpm6ZR+pz0Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783720513; c=relaxed/simple; bh=3y3GOvv88nZe1Tgh1BZjwdGD9qcA0l45lP8zkl5QVtE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=N3c+qIkDVjNssKuDBUF7t4gWBqD41xvMtCGuc/OvDLDvxRrx1vuCc8zSQWlyRt4rnok363WZxIK2lvTTW/u/HGRjUAvPThwpgF0Sb1e/lw5NsXAjmIfrYt+nYbHPR1+LIuo0JZRnuV86gM15o2xudenBR4VVMPs01TSL5y/NIVE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=aLrG0lVv; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="aLrG0lVv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1783720510; x=1815256510; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3y3GOvv88nZe1Tgh1BZjwdGD9qcA0l45lP8zkl5QVtE=; b=aLrG0lVvf/KhJEqkXrba0LmwzbNB9jJ9DXiiNMGvk4iZ3mJ/yLqZko9X dfdC+jUyiu3pH53yuzfQx07LG/xLD14YKwfz50HASj7FiWQQf1RQ6lMs5 DIhNgH0ozoSLQCag5fXkmpEHJLvJO+QXwKbopxqnMFu+/jwk8BF5d9apy sewLZj5uNeAKl83R+R+NtaGF/Vd/PAGJOsBKtvEqmPo8+kiWw94dO0DUz o8gYsi3pMXv6EJnnghbF7slBrHTz6Qi5Av/a+lAQZH5wp/pP1F9eYVK24 RwuuzVAGz+O/XOz85rS06IBtIJObPiPTSwFQObwe8zPHMqCEFo5lmQ9rs A==; X-CSE-ConnectionGUID: eoZ+qtfsSEixxd3oaeZWKA== X-CSE-MsgGUID: 4jCwKs4JSJO8EtFpy619Lg== X-IronPort-AV: E=McAfee;i="6800,10657,11841"; a="83543253" X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="83543253" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2026 14:54:57 -0700 X-CSE-ConnectionGUID: YcbAqTwVQNi97rST7Zeb3A== X-CSE-MsgGUID: PUUfqL/iTwuLC5pYVVi4NQ== X-ExtLoop1: 1 Received: from gsse-cloud1.jf.intel.com ([10.54.39.91]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2026 14:54:56 -0700 From: Matthew Brost To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Carlos Santa , Ryan Neph , Christian Koenig , Huang Rui , Matthew Auld , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org, =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= Subject: [PATCH v2 29/33] drm/xe: Add per-device dependency scheduler for IOVA defrag finalize Date: Fri, 10 Jul 2026 14:54:38 -0700 Message-Id: <20260710215442.2444235-30-matthew.brost@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260710215442.2444235-1-matthew.brost@intel.com> References: <20260710215442.2444235-1-matthew.brost@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A future patch performs the destination DMA mapping of a defrag move in two stages when the BO is IOVA mapped: a temporary contiguous mapping of just tht changed pages used for the GPU copy, followed by a post-copy finalize stet that tears that mapping down and links the new backing into the (transferred) IOVA reservation. The finalize step must run only after the GPU copy it depends on has completed, so it is dispatched as an xe_dep_job, Add a per-device xe_dep_scheduler dedicated to these finalize jobs, created in xe_bo_defrag_init() (after the migrate contexts are up) and torn down in xe_bo_defrag_fini(). No users yet; the job itself is added in a later patch. Cc: Carlos Santa Cc: Ryan Neph Cc: Christian Koenig Cc: Huang Rui Cc: Matthew Auld Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Thomas Zimmermann Cc: David Airlie Cc: Simona Vetter Cc: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org Cc: Thomas Hellström Assisted-by: GitHub_Copilot:claude-opus-4.8 Signed-off-by: Matthew Brost --- drivers/gpu/drm/xe/xe_bo.c | 15 +++++++++++++++ drivers/gpu/drm/xe/xe_device_types.h | 10 ++++++++++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c index f3d76ad9a105..ec034518e2ea 100644 --- a/drivers/gpu/drm/xe/xe_bo.c +++ b/drivers/gpu/drm/xe/xe_bo.c @@ -25,6 +25,7 @@ #include #include "xe_device.h" +#include "xe_dep_scheduler.h" #include "xe_dma_buf.h" #include "xe_drm_client.h" #include "xe_ggtt.h" @@ -1300,6 +1301,10 @@ static void xe_bo_defrag_fini(void *arg) struct xe_device *xe = arg; disable_delayed_work_sync(&xe->mem.defrag.worker); + if (xe->mem.defrag.iova_sched) { + xe_dep_scheduler_fini(xe->mem.defrag.iova_sched); + xe->mem.defrag.iova_sched = NULL; + } } /** @@ -1336,6 +1341,16 @@ void xe_bo_defrag_init_early(struct xe_device *xe) */ int xe_bo_defrag_init(struct xe_device *xe) { +#define XE_BO_MAX_IOVA_DEFRAG_JOBS 16 /* Picking a reasonable value */ + struct xe_dep_scheduler *iova_sched; + + iova_sched = xe_dep_scheduler_create(xe, NULL, "xe_iova_defrag", + XE_BO_MAX_IOVA_DEFRAG_JOBS); + if (IS_ERR(iova_sched)) + return PTR_ERR(iova_sched); + xe->mem.defrag.iova_sched = iova_sched; +#undef XE_BO_MAX_IOVA_DEFRAG_JOBS + return devm_add_action_or_reset(xe->drm.dev, xe_bo_defrag_fini, xe); } diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index 6e68add4d652..b55d549d5e30 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -38,6 +38,7 @@ struct drm_pagemap_shrinker; struct intel_display; +struct xe_dep_scheduler; struct intel_dg_nvm_dev; struct xe_ggtt; struct xe_i2c; @@ -325,6 +326,15 @@ struct xe_device { * @mem.defrag.worker, in milliseconds. */ unsigned int interval_ms; + /** + * @mem.defrag.iova_sched: Dependency scheduler used to + * run the post-copy IOVA finalize job for defrag moves + * of IOVA-mapped BOs. The job tears down the temporary + * copy-step IOVA mapping and links the new backing into + * the (transferred) reservation once the GPU copy that + * its dependencies gate has completed. + */ + struct xe_dep_scheduler *iova_sched; } defrag; } mem; -- 2.34.1