From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76A2E274FD0 for ; Sat, 11 Jul 2026 02:56:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783738589; cv=none; b=ZMyNSDKhq3QMg5NRVBsOBUygHApASDYWyPkyAE+UmzsegeHvQ6oZrCWl7PP831Xwtq5jGl6ZmEJvUBvfw42r0eTYtpgpf2VQeekDlFn+qfeJ04bcvY0cpIdQzLuamuIEjCKjiybl0zEybmrmXZJvnt2Rw3Nd6Gp6gb7F5hE3Rgs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783738589; c=relaxed/simple; bh=onB5KkS8J/1ab+CzHqV5dwJxkB3nLWQwKJ7ATOEu4QU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=mio8A7RPXKf51Wr82VuNLQJT0ebGoZNr/t5sIbaih8ufZkoRszadoJyWa7KWrVrBySFIt//5v5pPxlzw+qKW3r18CbBDUMUm+S8xk1/1kiqvj4NbTWCuNTCQSLPLZblTaKy3eTQi76t/EbvVHa5vBdDZus2YguytGemHiH/Fwkw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=PY3TsEpS; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PY3TsEpS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1783738588; x=1815274588; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=onB5KkS8J/1ab+CzHqV5dwJxkB3nLWQwKJ7ATOEu4QU=; b=PY3TsEpSp4ZR+EbXTVVUkjPp28e7ObqwI+CvPZh4EaJaGytPSOMZyBCc JOoBgvS9ISH3GigUM/cJN150Wej9yUJnAL24hQqxY4Cr/MlHFqFVk0jEk UjBjLOtUnmDQxAs6VKTHTb/jLtzXMlEayvjnNP4p1hFiX5YUzCA8F5VnA AONZQQ1Vp1Obs8XGx7/9uQ3XZfD8OF3pd37U4VFbHissp1EQsDnXWqrxd I+X1D4KYe5bKREfTkvIFfMTAj+ojj6jrbQZwrETYi+Ma07xqlEV0EnaEU xjplrymYtGksOt9xHeEvsdbX8j3D/cmrPOdI0K5hf5LjtxLXBfHspCvfq Q==; X-CSE-ConnectionGUID: WrKs7DLeS3W+wZUfwWCG+Q== X-CSE-MsgGUID: WDSjWlbxSliT2aNlgnoeRw== X-IronPort-AV: E=McAfee;i="6800,10657,11841"; a="101986185" X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="101986185" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2026 19:56:25 -0700 X-CSE-ConnectionGUID: YbFHngh2QMqIAfli62S5ig== X-CSE-MsgGUID: 88q3m20uQEyTE0+aUNrHZg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="256987679" Received: from gsse-cloud1.jf.intel.com ([10.54.39.91]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2026 19:56:24 -0700 From: Matthew Brost To: intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: Carlos Santa , Ryan Neph , Christian Koenig , Huang Rui , Matthew Auld , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org, =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= Subject: [PATCH v3 02/33] drm/ttm/pool: Add ttm_pool_page_order_nodma() helper Date: Fri, 10 Jul 2026 19:55:48 -0700 Message-Id: <20260711025619.2540575-3-matthew.brost@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260711025619.2540575-1-matthew.brost@intel.com> References: <20260711025619.2540575-1-matthew.brost@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TTM records the allocation order of a multi-order page in page->private at allocation time. For pools that do not use dma_alloc the order is stored directly, while dma_alloc pools store a struct ttm_pool_dma pointer there instead. Drivers that do their own DMA mapping (e.g. Xe) need the per-page order to walk a populated ttm_tt one chunk at a time, but cannot rely on folio_order(): TTM allocates high-order pages with alloc_pages_node() without __GFP_COMP, so they are not compound and folio_order() always returns 0. Expose ttm_pool_page_order_nodma(), a thin wrapper that returns the order recorded in page->private. It is only valid for pages from a pool that does not use dma_alloc; whether a TTM device uses dma_alloc is fixed at ttm device init time, so callers know from their device configuration that this helper applies. Use it from the existing internal ttm_pool_page_order() to keep a single source of truth. Cc: Carlos Santa Cc: Ryan Neph Cc: Christian Koenig Cc: Huang Rui Cc: Matthew Auld Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Thomas Zimmermann Cc: David Airlie Cc: Simona Vetter Cc: dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org Cc: Thomas Hellström Assisted-by: GitHub_Copilot:claude-opus-4.8 Signed-off-by: Matthew Brost --- drivers/gpu/drm/ttm/ttm_pool.c | 25 ++++++++++++++++++++++++- include/drm/ttm/ttm_pool.h | 2 ++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c index ab242ad4339e..5b7d7f5ae53d 100644 --- a/drivers/gpu/drm/ttm/ttm_pool.c +++ b/drivers/gpu/drm/ttm/ttm_pool.c @@ -461,6 +461,29 @@ static unsigned int ttm_pool_shrink(int nid, unsigned long num_to_free) return num_pages; } +/** + * ttm_pool_page_order_nodma() - Allocation order of a non-dma_alloc TTM page + * @p: The page to query. + * + * Return the allocation order that the TTM pool allocator recorded in + * @p->private at allocation time. This only works for pages that were + * allocated from a pool which does *not* use dma_alloc (i.e. pages backed by + * alloc_pages_node()), where TTM stores the order directly in page->private. + * + * For dma_alloc pools, page->private instead holds a struct ttm_pool_dma + * pointer and this helper must not be used. Whether a TTM device uses + * dma_alloc is fixed at ttm device init time, so callers are expected to know + * from their TTM device configuration that their pages are not dma_alloc + * backed before using this helper. + * + * Return: The allocation order of the page. + */ +unsigned int ttm_pool_page_order_nodma(struct page *p) +{ + return p->private; +} +EXPORT_SYMBOL(ttm_pool_page_order_nodma); + /* Return the allocation order based for a page */ static unsigned int ttm_pool_page_order(struct ttm_pool *pool, struct page *p) { @@ -470,7 +493,7 @@ static unsigned int ttm_pool_page_order(struct ttm_pool *pool, struct page *p) return dma->vaddr & ~PAGE_MASK; } - return p->private; + return ttm_pool_page_order_nodma(p); } /* diff --git a/include/drm/ttm/ttm_pool.h b/include/drm/ttm/ttm_pool.h index 26ee592e1994..753203980e2c 100644 --- a/include/drm/ttm/ttm_pool.h +++ b/include/drm/ttm/ttm_pool.h @@ -94,6 +94,8 @@ long ttm_pool_backup(struct ttm_pool *pool, struct ttm_tt *ttm, int ttm_pool_restore_and_alloc(struct ttm_pool *pool, struct ttm_tt *tt, const struct ttm_operation_ctx *ctx); +unsigned int ttm_pool_page_order_nodma(struct page *p); + int ttm_pool_mgr_init(unsigned long num_pages); void ttm_pool_mgr_fini(void); -- 2.34.1