From: Jason Gunthorpe <jgg@nvidia.com>
To: Pranjal Shrivastava <praan@google.com>
Cc: Nicolin Chen <nicolinc@nvidia.com>, Will Deacon <will@kernel.org>,
Kevin Tian <kevin.tian@intel.com>,
Lu Baolu <baolu.lu@linux.intel.com>,
Robin Murphy <robin.murphy@arm.com>,
joro@8bytes.org, David Woodhouse <dwmw2@infradead.org>,
linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 1/5] iommu/arm-smmu-v3-iommufd: Reject unsupported bits in invalidation commands
Date: Tue, 14 Jul 2026 09:14:51 -0300 [thread overview]
Message-ID: <20260714121451.GJ674038@nvidia.com> (raw)
In-Reply-To: <alYC3bNbXY9l0eVn@google.com>
On Tue, Jul 14, 2026 at 09:35:25AM +0000, Pranjal Shrivastava wrote:
> > + u8 ttl = FIELD_GET(CMDQ_TLBI_1_TTL, cmd->cmd.data[1]);
> > + u8 tg = FIELD_GET(CMDQ_TLBI_1_TG, cmd->cmd.data[1]);
> > +
> > + /* NUM, SCALE and TTL are RES0 when TG == 0 */
> > + if (!tg)
> > + return (range || ttl) ? -EIO : 0;
> > + /* TTL == 0b01 with a 16KB TG requires SMMU_IDR5.DS */
> > + if (tg == 2 && ttl == 1 && !(smmu->features & ARM_SMMU_FEAT_DS))
>
> I agree we must check this but I'm a little confused, How is a user /
> VMM depending on the IDR5.DS bit today? The IDR5 is exposed to the user
> via hw_info AND in the uAPI documentation block we explicitly mention
> for struct iommu_hw_info_arm_smmuv3 the following valid fields for IDR5:
>
> idr[5]: VAX, GRAN64K, GRAN16K, GRAN4K
Probably soon we will add DS to that comment and it will be fully
backwards compatible so a new VMM following the new guidance can just
read DS.
Thus we can't have any kernel release that doesn't work with a VMM
following DS...
Jason
next prev parent reply other threads:[~2026-07-14 12:14 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-08 19:44 [PATCH v3 0/5] iommufd: Iterate the cache invalidation array in the core Nicolin Chen
2026-07-08 19:44 ` [PATCH v3 1/5] iommu/arm-smmu-v3-iommufd: Reject unsupported bits in invalidation commands Nicolin Chen
2026-07-14 9:35 ` Pranjal Shrivastava
2026-07-14 12:14 ` Jason Gunthorpe [this message]
2026-07-14 13:00 ` Pranjal Shrivastava
2026-07-08 19:44 ` [PATCH v3 2/5] iommufd: Iterate the cache invalidation array in the core Nicolin Chen
2026-07-13 5:58 ` Baolu Lu
2026-07-14 12:29 ` Pranjal Shrivastava
2026-07-08 19:44 ` [PATCH v3 3/5] iommufd/selftest: Convert cache invalidation mocks to the core array loop Nicolin Chen
2026-07-14 13:06 ` Pranjal Shrivastava
2026-07-08 19:44 ` [PATCH v3 4/5] iommu/arm-smmu-v3-iommufd: Convert cache invalidation " Nicolin Chen
2026-07-14 13:33 ` Pranjal Shrivastava
2026-07-08 19:44 ` [PATCH v3 5/5] iommu/vt-d: Convert nested " Nicolin Chen
2026-07-13 5:58 ` Baolu Lu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260714121451.GJ674038@nvidia.com \
--to=jgg@nvidia.com \
--cc=baolu.lu@linux.intel.com \
--cc=dwmw2@infradead.org \
--cc=iommu@lists.linux.dev \
--cc=joro@8bytes.org \
--cc=kevin.tian@intel.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=nicolinc@nvidia.com \
--cc=praan@google.com \
--cc=robin.murphy@arm.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox