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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SN1PEPF000397AE.mail.protection.outlook.com (10.167.248.52) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.270.5 via Frontend Transport; Mon, 27 Jul 2026 13:31:52 +0000 Received: from purico-ed03host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Mon, 27 Jul 2026 08:31:43 -0500 From: Suravee Suthikulpanit To: , , , CC: , , , , , , , , , , , , , , , "Suravee Suthikulpanit" Subject: [PATCH 19/24] iommu/amd: Add per-segment translate device ID pool Date: Mon, 27 Jul 2026 13:29:08 +0000 Message-ID: <20260727132913.22475-20-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260727132913.22475-1-suravee.suthikulpanit@amd.com> References: <20260727132913.22475-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AE:EE_|SA0PR12MB4430:EE_ X-MS-Office365-Filtering-Correlation-Id: 34c13a2e-ea41-4995-2a78-08deebe36b81 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|23010399003|376014|7416014|1800799024|36860700016|18002099003|10067099003|22082099003|56012099006|11063799006; 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The pool is per-segment because the AMD IOMMU device table is per-segment. Add amd_iommu_pci_seg_trans_devid_init/fini() during segment setup and teardown, amd_iommu_trans_devid_reserve() for attach-time reservation, and trans_devid.c implementing the xarray-backed pool. Allocated slots are recorded as pointers to the owning vIOMMU once allocation is added. Call the reserve hook from amd_iommu_attach_device() before programming the DTE. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/Makefile | 2 +- drivers/iommu/amd/amd_iommu.h | 12 +++++ drivers/iommu/amd/amd_iommu_types.h | 17 +++++++ drivers/iommu/amd/init.c | 3 ++ drivers/iommu/amd/iommu.c | 12 +++++ drivers/iommu/amd/trans_devid.c | 78 +++++++++++++++++++++++++++++ 6 files changed, 123 insertions(+), 1 deletion(-) create mode 100644 drivers/iommu/amd/trans_devid.c diff --git a/drivers/iommu/amd/Makefile b/drivers/iommu/amd/Makefile index e1e824b9c7b0..12c3fe83e4ce 100644 --- a/drivers/iommu/amd/Makefile +++ b/drivers/iommu/amd/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y += iommu.o init.o quirks.o ppr.o pasid.o -obj-$(CONFIG_AMD_IOMMU_IOMMUFD) += iommufd.o nested.o viommu.o +obj-$(CONFIG_AMD_IOMMU_IOMMUFD) += iommufd.o nested.o viommu.o trans_devid.o obj-$(CONFIG_AMD_IOMMU_DEBUGFS) += debugfs.o diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 951757c2507f..284830673a87 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -218,6 +218,18 @@ void amd_iommu_update_dte(struct amd_iommu *iommu, struct dev_table_entry *new); int amd_iommu_completion_wait(struct amd_iommu *iommu); +/* Per-segment translate-device-id pool (CONFIG_AMD_IOMMU_IOMMUFD) */ +#ifdef CONFIG_AMD_IOMMU_IOMMUFD +void amd_iommu_pci_seg_trans_devid_init(struct amd_iommu_pci_seg *pci_seg); +void amd_iommu_pci_seg_trans_devid_fini(struct amd_iommu_pci_seg *pci_seg); +int amd_iommu_trans_devid_reserve(struct amd_iommu_pci_seg *pci_seg, u16 id); +#else +static inline void +amd_iommu_pci_seg_trans_devid_init(struct amd_iommu_pci_seg *pci_seg) { } +static inline void +amd_iommu_pci_seg_trans_devid_fini(struct amd_iommu_pci_seg *pci_seg) { } +#endif + static inline void amd_iommu_make_clear_dte(struct amd_iommu *iommu, u16 devid, struct dev_table_entry *new) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 39aa872c2741..c102d059964a 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -612,6 +612,13 @@ PT_IOMMU_CHECK_DOMAIN(struct protection_domain, iommu, domain); PT_IOMMU_CHECK_DOMAIN(struct protection_domain, amdv1.iommu, domain); PT_IOMMU_CHECK_DOMAIN(struct protection_domain, amdv2.iommu, domain); +#ifdef CONFIG_AMD_IOMMU_IOMMUFD +enum trans_devid_state { + TRANS_DEVID_FREE = 0, + TRANS_DEVID_RESERVED, +}; +#endif + /* * This structure contains information about one PCI segment in the system. */ @@ -673,6 +680,16 @@ struct amd_iommu_pci_seg { * parsing time. */ struct list_head unity_map; + +#ifdef CONFIG_AMD_IOMMU_IOMMUFD + /* + * Per-segment translate-device-id pool indexed by id. Entries are: + * absent (FREE), xa value TRANS_DEVID_RESERVED, or a pointer to the + * owning struct amd_iommu_viommu (ALLOCATED). + */ + struct mutex trans_devid_mutex; + struct xarray trans_devid_xa; +#endif }; /* diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 6e69b3dd8b1e..622bc0337eda 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -1737,6 +1737,8 @@ static struct amd_iommu_pci_seg *__init alloc_pci_segment(u16 id, if (alloc_rlookup_table(pci_seg)) goto err_free_alias_table; + amd_iommu_pci_seg_trans_devid_init(pci_seg); + return pci_seg; err_free_alias_table: @@ -1768,6 +1770,7 @@ static void __init free_pci_segments(void) for_each_pci_segment_safe(pci_seg, next) { list_del(&pci_seg->list); + amd_iommu_pci_seg_trans_devid_fini(pci_seg); free_irq_lookup_table(pci_seg); free_rlookup_table(pci_seg); free_alias_table(pci_seg); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 6895629cc8a5..02b3d3c19936 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3069,6 +3069,18 @@ static int amd_iommu_attach_device(struct iommu_domain *dom, struct device *dev, if (dom->dirty_ops && !amd_iommu_hd_support(iommu)) return -EINVAL; +#if IS_ENABLED(CONFIG_AMD_IOMMU_IOMMUFD) + /* Translate-device-id reservation must be done before setting up + * the DTE for the device to make sure that the id has not been allocated + * yet. (See amd_iommu_trans_devid_alloc().) + */ + ret = amd_iommu_trans_devid_reserve(iommu->pci_seg, dev_data->devid); + if (ret) { + pr_err("%s: Failed to reserve device id %#x\n", __func__, dev_data->devid); + return ret; + } +#endif + if (dev_data->domain) detach_device(dev); diff --git a/drivers/iommu/amd/trans_devid.c b/drivers/iommu/amd/trans_devid.c new file mode 100644 index 000000000000..42ab19180e1c --- /dev/null +++ b/drivers/iommu/amd/trans_devid.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Advanced Micro Devices, Inc. + * + * AMD vIOMMU translate-device-id management. + * + * The pool is per PCI segment because the AMD IOMMU device table is + * per-segment. Each id must be allocated from unused slots in that + * segment. It is used to program the vIOMMU VF Control register to + * specify the DTE used to contain the GPA->SPA mapping (v1 page table). + */ + +#include +#include + +#include "amd_iommu.h" + +static inline bool trans_devid_xa_is_reserved(void *entry) +{ + return entry && xa_is_value(entry) && + xa_to_value(entry) == TRANS_DEVID_RESERVED; +} + +static inline void *trans_devid_xa_mk_reserved(void) +{ + return xa_mk_value(TRANS_DEVID_RESERVED); +} + +static int trans_devid_xa_install_reserved_locked(struct amd_iommu_pci_seg *pci_seg, + u16 id) +{ + void *old; + + old = xa_store(&pci_seg->trans_devid_xa, id, + trans_devid_xa_mk_reserved(), GFP_KERNEL); + if (xa_is_err(old)) + return xa_err(old); + WARN_ON_ONCE(old); + return 0; +} + +void amd_iommu_pci_seg_trans_devid_init(struct amd_iommu_pci_seg *pci_seg) +{ + mutex_init(&pci_seg->trans_devid_mutex); + xa_init(&pci_seg->trans_devid_xa); +} + +void amd_iommu_pci_seg_trans_devid_fini(struct amd_iommu_pci_seg *pci_seg) +{ + xa_destroy(&pci_seg->trans_devid_xa); +} + +/** + * amd_iommu_trans_devid_reserve - occupy @id so it is never returned by alloc + * + * Reservation is done when attaching device to a domain (see amd_iommu_attach_device()). + * + * Return: 0 on success. A second reserve of an already-reserved @id succeeds. + */ +int amd_iommu_trans_devid_reserve(struct amd_iommu_pci_seg *pci_seg, u16 id) +{ + void *entry; + int ret = 0; + + mutex_lock(&pci_seg->trans_devid_mutex); + entry = xa_load(&pci_seg->trans_devid_xa, id); + if (trans_devid_xa_is_reserved(entry)) + goto unlock; + + ret = trans_devid_xa_install_reserved_locked(pci_seg, id); +unlock: + mutex_unlock(&pci_seg->trans_devid_mutex); + + if (!ret) + pr_debug("%s: Reserved trans_devid %#x (seg %#x)\n", __func__, id, + pci_seg->id); + return ret; +} -- 2.34.1