From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ot1-f41.google.com (mail-ot1-f41.google.com [209.85.210.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 428973EE1D1 for ; Tue, 28 Jul 2026 07:31:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.41 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785223918; cv=none; b=gNDpBvrPZijX76a+9gbndvj6dBTsf9/LGjfR3cDIK7UM0ZsmObRxGTF4L75EwAjbCsWRMpwHLWQsD3GZ3uxv/yVtengIn4s8kjFjSS80zl6MhFa1iVeH5SvQ/Pg7nI/WimglCh4f+wuTE6F0cexLKCdUaQkU0aibu6PnW3N2wio= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785223918; c=relaxed/simple; bh=nHz26HyX2icLFETYR9Iev6Jeil3DeEl+pOtquaWQhWI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TwS9w287xF/KDEP+f72GDXu8wVeReExeJw3Efrv6fb2CXoLvHer+oaEq91MfPk1/wa66BWf3kTtLuaQWVqkyqB7O1tecWu64IX9HQFbo8zvDgbK2glLgQ/KcL+ysfzqk4g1lbgpjuCGu/tpto5X7FamAFppeW+LvTXnKbYEbCBY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=manifault.com; spf=pass smtp.mailfrom=manifault.com; dkim=pass (2048-bit key) header.d=manifault-com.20251104.gappssmtp.com header.i=@manifault-com.20251104.gappssmtp.com header.b=eBUiDwtn; arc=none smtp.client-ip=209.85.210.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=manifault.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=manifault.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=manifault-com.20251104.gappssmtp.com header.i=@manifault-com.20251104.gappssmtp.com header.b="eBUiDwtn" Received: by mail-ot1-f41.google.com with SMTP id 46e09a7af769-7ee37dc91f5so2079603a34.3 for ; Tue, 28 Jul 2026 00:31:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=manifault-com.20251104.gappssmtp.com; s=20251104; t=1785223916; x=1785828716; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=l5A0TG1ydLAI7SFr9to4UPVUQL8Gvvi1TATrMVTL7lw=; b=eBUiDwtnvdrs0NllzmxWMNYrNHjQ1q5ztSZhJ5XmgRyFwFIhEa5B+tGai7ezrw8kc4 Yt8Tuv62yeCzwb/PFoV8DkPYNHVTZX/PM8X8fInyNYZsZxQKiyU/Hz622zxA+5flmx7Y 9nkNUr1qZYgbfCAKV5k+WejjFY5tyEh7W7VjcVMOfJnSOQOkHRMJleoft4sbOIIVjfk1 EEi87pvuEIF4xdah+J6/tOY7U/ksoXKmqmZnM6jsaS+Z7sIffC8Q9Pp7JXr8WWR9FWqZ ERD2EdEirfz3kqI0/Ri8VCMJmzEAMpufq1/91yYuGsmgLEKXIGb/ABRp4HoPbU4XlhZy M2bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785223916; x=1785828716; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=l5A0TG1ydLAI7SFr9to4UPVUQL8Gvvi1TATrMVTL7lw=; b=jmZJE4cE+OTrIj51n71qbUon0+SVDL5Otnqeba4gfn7xu+WmgFRxHg+BYnMRpom/ys q4cbnjXxfcEAOsNBNjXmXPb71V0Rq9dZ8ZccPguxgBNbElCC7vZXl6kNC64ugtaXeXVl d2lsFnbd62vDHEK4zzz59cI/MDtzbtGtkPSW9Q4Uiy7wU62YxFKYnH5FJljStSY7j7Ff zI5sVgUSfsIaYn8XeFSv5ZXXOAnjlljhJGeoS9qqqR+dT0vS9teF3fpsCMzfO0hPII23 Q3mKp/0hHfUPGrNn6py5w5QB5UYOgcDhidtVEXZUnmvvw78I/r3XZhNV1oRThR0bLdqR ayWg== X-Forwarded-Encrypted: i=1; AHgh+Ros5M5ZraqeEbLcCZFEXTnF/9UdJOqwmLSXDWT2jX3mKbstyducbdgPF+9KfuWe2ZS/gP5R5E1o++kCEC8=@vger.kernel.org X-Gm-Message-State: AOJu0YxSfYi9YeQSoKKXbpGknBMl4pa1yKLznZ3R54jMdkxwpuw3afge 3BttamTB7/go9PXTUv+BGJrtAjsVJ9DDjw6qiLARa1+NyGctKdnyXR9IPcOUYf5iHk3/ X-Gm-Gg: AR+sD12/YSvtf1skJH2fyobr7ZJqy4QMrB4qjVRb4LY6eoyIJbRWo8HgFEgg1ThxKyz hQoGwFRXsVxZBPPTmhIV9EwIoNM/udyOjgGt21xfxm/cQitYFi8zsjVj9jfirBCUfbrDli8/3kp eZau2EViBi01qwPIxn0yxRkTifGQRvXAsGzf+Ej7xpWy98dg2W0x5s1xzLN4LLiK8UcyA+L9GmD KK1Ix0W5chziZM+apTtWSdakUs5B284RNkJxJ8KXC1yqsz2z+Qh4tu8Kf79Yt/qS2bWL5YWXVGm Tc1kdO7x5a1kEZqF/ZG9TMBk6JoAg9TwhHp7XeiVllnWZlO3QM+BGfAM9FUytGm+KgDGB13tF/7 ZzoWK8XgKATEurxIn8jRBtkgovbbmoxufTYBjjnHbQ09qzQPNcJX7ZkU82WszFrLU+0ypZPg3Vx VQY/LFl30Kg7IhaJE32AD89h5gTmq3Te8CWsr6pQ== X-Received: by 2002:a05:6830:928:b0:7e9:5022:3639 with SMTP id 46e09a7af769-7efff036be0mr1163450a34.15.1785223916145; Tue, 28 Jul 2026 00:31:56 -0700 (PDT) Received: from localhost (c-76-141-129-107.hsd1.il.comcast.net. [76.141.129.107]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7ee2a108679sm14304390a34.27.2026.07.28.00.31.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2026 00:31:55 -0700 (PDT) From: David Vernet To: "Rafael J. Wysocki" Cc: Mario Limonciello , "Gautham R. Shenoy" , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Andr=C3=A9=20Almeida?= , Changwoo Min Subject: [RFC PATCH 2/4] cpufreq/amd-pstate: Update cppc_req_cached before writing the MSR Date: Tue, 28 Jul 2026 02:31:48 -0500 Message-ID: <20260728073150.54964-3-void@manifault.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260728073150.54964-1-void@manifault.com> References: <20260728073150.54964-1-void@manifault.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit msr_update_perf() and msr_set_epp() currently write MSR_AMD_CPPC_REQ first and update cppc_req_cached only after the write succeeds. This leaves a window in which the MSR holds the new request while the cache holds the previous one. That's fine right now, but a subsequent patch will add a per-core EPP boost that runs from scheduling context and mutates that MSR from the contents of the cached value. If we update the cache after writing the MSR, the sched callback could run between the wrmsrq and the cache being updated, and accidentally overwrite the intended value of the MSR by issuing a wrmsrq on the stale cached value. To avoid this, let's update the cache prior to the MSR write, as is done in intel_pstate_set_epp(). This should be a functional no-op. Signed-off-by: David Vernet --- drivers/cpufreq/amd-pstate.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 6e255a22a0b8..5d7debb5a35c 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -262,17 +262,19 @@ static int msr_update_perf(struct cpufreq_policy *policy, u8 min_perf, if (value == prev) return 0; + WRITE_ONCE(cpudata->cppc_req_cached, value); + if (fast_switch) { wrmsrq(MSR_AMD_CPPC_REQ, value); } else { int ret = wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); - if (ret) + if (ret) { + WRITE_ONCE(cpudata->cppc_req_cached, prev); return ret; + } } - WRITE_ONCE(cpudata->cppc_req_cached, value); - return 0; } @@ -312,16 +314,16 @@ static int msr_set_epp(struct cpufreq_policy *policy, u8 epp) if (value == prev) return 0; + WRITE_ONCE(cpudata->cppc_req_cached, value); + ret = wrmsrq_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); if (ret) { + WRITE_ONCE(cpudata->cppc_req_cached, prev); pr_err("failed to set energy perf value (%d)\n", ret); return ret; } - /* update both so that msr_update_perf() can effectively check */ - WRITE_ONCE(cpudata->cppc_req_cached, value); - - return ret; + return 0; } DEFINE_STATIC_CALL(amd_pstate_set_epp, msr_set_epp); -- 2.53.0