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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fb6b189f0sm1044847f8f.26.2026.07.28.11.56.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2026 11:56:14 -0700 (PDT) Date: Tue, 28 Jul 2026 19:56:11 +0100 From: David Laight To: Dave Hansen Cc: "Chang S. Bae" , Sohil Mehta , "Maciej W. Rozycki" , linux-kernel@vger.kernel.org, x86@kernel.org, tglx@kernel.org, Ingo Molnar , bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com Subject: Re: [PATCH] x86/microcode/intel: Panic on partial microcode update Message-ID: <20260728195611.5d41ee5a@pumpkin> In-Reply-To: <9762ae8a-70e9-4376-a6fe-a05d05721a23@intel.com> References: <20260630191350.3837-1-chang.seok.bae@intel.com> <4f2a4841-0a73-4f44-aec8-890734660a9c@intel.com> <12374cc0-aa93-409f-8108-7e9f5d7160e1@intel.com> <9762ae8a-70e9-4376-a6fe-a05d05721a23@intel.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Tue, 28 Jul 2026 07:12:13 -0700 Dave Hansen wrote: > On 7/27/26 19:58, Chang S. Bae wrote: > > In this new state, the processor may either continue operating or end up > > running with a combination of sub-components that has never been tested. > > Given that, I think one question to ask in the end is whether we trust > > the microcode's own error handling (completely), or not. > > We *have* to trust it completely. > > Think of it like this: CPUs are fundamentally analog, physical things. > They malfunction. They break. They include human-induced design errors. > But we don't have all kinds of code in the kernel to make sure that > gates in the ALU don't go bonkers and do 1+1=3. > > It's not because kernel developers don't think that CPUs can break. It's > because if we went trying to detect things like that ^, the kernel > wouldn't be able to do anything else useful. > > It's the same for the microcode update. The kernel first trusts that the > CPU does what the spec says. If that turns out not to be enough in the > real world, the kernel adds some paranoia later. But it's done > defensively against real, actual screwups. Not preemptively against > every imaginable screwup. > > WARN(), please. Not panic(). > PANIC_ON_WARN ....