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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49764d6d0f8sm8998665e9.2.2026.07.28.15.05.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2026 15:05:05 -0700 (PDT) Date: Tue, 28 Jul 2026 23:05:04 +0100 From: David Laight To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, ada.coupriediaz@arm.com, ardb@kernel.org, catalin.marinas@arm.com, hca@linux.ibm.com, linux-kernel@vger.kernel.org, maz@kernel.org, peterz@infradead.org, ruanjinjie@huawei.com, vladimir.murzin@arm.com, will@kernel.org, yang@os.amperecomputing.com Subject: Re: [RFC PATCH 07/13] arm64: percpu: Implement preemptible read/write ops Message-ID: <20260728230504.41e2861a@pumpkin> In-Reply-To: <20260728123859.2911495-8-mark.rutland@arm.com> References: <20260728123859.2911495-1-mark.rutland@arm.com> <20260728123859.2911495-8-mark.rutland@arm.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Tue, 28 Jul 2026 13:38:53 +0100 Mark Rutland wrote: > Use the PCPU GPR infrastructure to implement preemptible this_cpu_read() > and this_cpu_write(). > > Note that this change means that this_cpu_read() will always use a plain > LDR, even in LTO configurations where READ_ONCE() will use LDA[P]R. I > am not sure whether that's ok, or whether we should similarly use > LDA[P]R here. > ... > Generated code after this patch: > > | : > | mrs x2, sp_el0 > | mov w3, #0x7c60 > | strh w3, [x2, #20] > | mrs x3, tpidr_el1 > | str x1, [x0, x3] > | strh wzr, [x2, #20] > | ret How is that likely to get scheduled on a typical arm64 cpu? In particular does the reuse of [wx]3 create a register dependency between the two instruction flows and stop then running in parallel. A typical x86 cpu (that anyone cares about) does register renaming so it wouldn't matter, but I don't know about arm. So it might be worth using different register for w3 and x3 (although that might cause a spill - which will be worse). David