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Thu, 30 Jul 2026 12:13:41 -0700 (PDT) X-Received: by 2002:a17:903:2f8f:b0:2ce:b8c5:5de3 with SMTP id d9443c01a7336-2d035e50f61mr33614395ad.36.1785438820777; Thu, 30 Jul 2026 12:13:40 -0700 (PDT) Received: from localhost ([50.35.46.84]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-31504dab154sm26198193eec.26.2026.07.30.12.13.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 12:13:40 -0700 (PDT) Date: Thu, 30 Jul 2026 12:13:36 -0700 From: Jonathan Cameron To: Andre Przywara Cc: Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu , Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , Lee Trager , Ritwick Sharma , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 09/10] arm_mpam: change MPAM-Fb error IRQ to use a threaded IRQ handler Message-ID: <20260730121336.00002130@oss.qualcomm.com> In-Reply-To: <20260730152539.2712312-10-andre.przywara@arm.com> References: <20260730152539.2712312-1-andre.przywara@arm.com> <20260730152539.2712312-10-andre.przywara@arm.com> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMwMDE0MSBTYWx0ZWRfXzDBzbNs9xx2Q 09bZ2H9nrqJ5Dbh147X9FXPvfbbdgDpiW84w991H2/GF0/pvT/dIXHgC5fiRSoSn1mtEKVOObDO rFRNXJUwmOSx8je1L4PLqg2UfSyuUzI= X-Authority-Analysis: v=2.4 cv=A5xc+aWG c=1 sm=1 tr=0 ts=6a6ba265 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=qC1CW/w66vtJz1P9yTJxNA==:17 a=kj9zAlcOel0A:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=7CQSdrXTAAAA:8 a=Ah_BjpGRzk7GCQLzXeIA:9 a=CjuIK1q_8ugA:10 a=uG9DUKGECoFWVXl0Dc02:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMwMDE0MSBTYWx0ZWRfX7BHi9UQBYQw0 JyDwaJ1kB8TOY51thWDFWYbB3JtBrPrCTArkAiEWBPgbEnl/dpqsReMct64+yWEx883FflhxHgG R784ArqozfO+k5sJgULa+sNyaCc/1dRWVPRi+hYv9oGbOmFlddXZVwkY/DZeWc1nHrSYKj6rf43 hSH/+bzSZpI/kWTSTQzJ7WffYTkDB2Nn23C9t0iti/mSzDlAqFmVtiD2tYDhLvghP/Od6rSMnBk B0DTidmauamijWpQzHtNrdj5qMJEuvykaYv78Zqx5gOkYksEwzdEykfj80WdyPJjmNBbcUJpDiO hK0CyjbXWcO7Ry0HQrkYpO6+YG5ODfGE0LuxRJ79A8M7ikHGnPIs3YDFiV1BUy+KXuwr6H/Xjry WP2g+V/txzQJ2s1BBMlZ1pcPROLpum1Mw+m+BoHKAYNjnIuMhDPogv0sv8bQ+xlw52H3F5qkR3B yNqJDtXt6Qe9w/TOn4g== X-Proofpoint-ORIG-GUID: UPJaMAyPAHB49JhDGuLm-U83Q9-fcJNi X-Proofpoint-GUID: UPJaMAyPAHB49JhDGuLm-U83Q9-fcJNi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-30_05,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 malwarescore=0 clxscore=1015 suspectscore=0 priorityscore=1501 impostorscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607300141 On Thu, 30 Jul 2026 17:25:38 +0200 Andre Przywara wrote: > When an MPAM MSC gets into an error condition, it can trigger an error > IRQ. We cannot really do much about those errors, but we at least query > and log the error, then disable MPAM functionality. > > This error report relies on reading the MSC's error status register > (ESR) in the current hard-IRQ handler, which is not possible for MPAM-Fb > based MSC accesses, since they involve mailbox routines that might sleep. > The same is true for clearing the interrupt at the source, which requires > an MSC access as well. > > When an MSC is using MPAM-Fb, change the error IRQ to use a threaded IRQ > handler, with an empty hard IRQ routine, and doing all the MSC accesses > (to access the status and disable the IRQ line) in the threaded part. > The change is minimal, we just check for the first MSC access error and > bail out early. MMIO based MSCs keep using a hard-IRQ handler, since > they must be at least non-migrate-able when doing MSC accesses, for the > CPU affinity check to work. > Also forbid per-CPU interrupts (PPIs) for MPAM-Fb, as we cannot use a > threaded IRQ here. > > Signed-off-by: Andre Przywara One thing below. > --- > drivers/resctrl/mpam_devices.c | 64 ++++++++++++++++++++++++++-------- > 1 file changed, 49 insertions(+), 15 deletions(-) > > diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c > index daaf3cf48475..606ae4af2be9 100644 > --- a/drivers/resctrl/mpam_devices.c > +++ b/drivers/resctrl/mpam_devices.c > @@ -2747,9 +2766,24 @@ static int mpam_register_irqs(void) > &_enable_percpu_irq, &irq, > true); > } else { > - err = devm_request_irq(&msc->pdev->dev, irq, > - &mpam_spi_handler, IRQF_SHARED, > - "mpam:msc:error", msc); > + irq_handler_t hard, threaded; > + > + /* > + * MPAM-Fb needs a sleepable context for the MSC > + * accesses, whereas MMIO requires at least a > + * non-migrateable context for the processor ID check. > + */ > + if (msc->iface == MPAM_IFACE_MMIO) { > + hard = &mpam_spi_handler; > + threaded = NULL; > + } else { > + hard = NULL; > + threaded = &mpam_spi_handler; > + } > + err = devm_request_threaded_irq(&msc->pdev->dev, irq, > + hard, threaded, > + IRQF_SHARED | IRQF_ONESHOT, IIRC correctly you'll trip a warning message for the case of MMIO and marking it as IRQF_ONESHOT. See __setup_irq() That was a fairly recent check to be added and caused all sorts of problems with cases similar to this one where the handlers are coming from variables. Upshot, you need to call appropriate registration function. Jonathan > + "mpam:msc:error", msc); > if (err) > return err; > }