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Thu, 30 Jul 2026 18:21:37 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e35]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38facf50124sm198867a91.3.2026.07.30.18.21.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Jul 2026 18:21:36 -0700 (PDT) From: Rosen Penev To: linux-edac@vger.kernel.org Cc: Frank Li , Borislav Petkov , Tony Luck , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , York Sun , imx@lists.linux.dev (open list:EDAC-FSL_DDR), linux-kernel@vger.kernel.org (open list), llvm@lists.linux.dev (open list:CLANG/LLVM BUILD SUPPORT:Keyword:\b(?i:clang|llvm)\b) Subject: [PATCHv2 3/3] EDAC/fsl_ddr: restore MC error registers on probe failure Date: Thu, 30 Jul 2026 18:21:30 -0700 Message-ID: <20260731012130.1212640-4-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260731012130.1212640-1-rosenp@gmail.com> References: <20260731012130.1212640-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit fsl_mc_err_probe() clears FSL_MC_ERR_DISABLE and, in EDAC_OPSTATE_INT mode, sets FSL_MC_ERR_INT_EN to enable error reporting. If a later initialization step fails and jumps to the err/err2 labels, the cleanup only frees driver memory and does not restore these hardware registers. This leaves the memory controller configured to generate interrupts while no handler is successfully registered, which can cause an unhandled interrupt storm on the shared IRQ line. Restore FSL_MC_ERR_DISABLE, FSL_MC_ERR_INT_EN and the SBE threshold in both error paths. Do not pre-initialize orig_ddr_err_disable/orig_ddr_err_sbe to 0; the err path must only restore registers that were actually modified. Split the error labels so early failures (before the first hardware write at line ~~580) jump to err_free, which does cleanup without touching hardware registers. Save orig_ddr_err_sbe alongside orig_ddr_err_disable so the err label correctly restores both registers, avoiding stale bootloader state clobbers. Built for arm64 (defconfig + CONFIG_EDAC_FSL_DDR) with LLVM=1; drivers/edac/fsl_ddr_edac.o compiles cleanly. Fixes: ea2eb9a8b620 ("EDAC, fsl-ddr: Separate FSL DDR driver from MPC85xx") Assisted-by: opencode:hy3-free Signed-off-by: Rosen Penev --- drivers/edac/fsl_ddr_edac.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c index c505fb268474..139277c4e2f0 100644 --- a/drivers/edac/fsl_ddr_edac.c +++ b/drivers/edac/fsl_ddr_edac.c @@ -577,23 +577,22 @@ int fsl_mc_err_probe(struct platform_device *op) pdata->orig_ddr_err_disable = ddr_in32(pdata, FSL_MC_ERR_DISABLE); ddr_out32(pdata, FSL_MC_ERR_DISABLE, 0); + /* store the original SBE threshold */ + pdata->orig_ddr_err_sbe = ddr_in32(pdata, FSL_MC_ERR_SBE) & 0xff0000; + /* clear all error bits */ ddr_out32(pdata, FSL_MC_ERR_DETECT, ~0); res = edac_mc_add_mc_with_groups(mci, fsl_ddr_dev_groups); if (res) { edac_dbg(3, "failed edac_mc_add_mc()\n"); - goto err; + goto err1; } if (edac_op_state == EDAC_OPSTATE_INT) { ddr_out32(pdata, FSL_MC_ERR_INT_EN, DDR_EIE_MBEE | DDR_EIE_SBEE); - /* store the original error management threshold */ - pdata->orig_ddr_err_sbe = ddr_in32(pdata, - FSL_MC_ERR_SBE) & 0xff0000; - /* set threshold to 1 error per interrupt */ ddr_out32(pdata, FSL_MC_ERR_SBE, 0x10000); @@ -621,6 +620,11 @@ int fsl_mc_err_probe(struct platform_device *op) err2: edac_mc_del_mc(&op->dev); + ddr_out32(pdata, FSL_MC_ERR_INT_EN, 0); +err1: + ddr_out32(pdata, FSL_MC_ERR_DISABLE, + pdata->orig_ddr_err_disable); + ddr_out32(pdata, FSL_MC_ERR_SBE, pdata->orig_ddr_err_sbe); err: edac_mc_free(mci); return res; -- 2.55.0