From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8960D3C5523 for ; Sun, 2 Aug 2026 16:53:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785689622; cv=none; b=f5egRhaDDDEqA8cyAUavYqX/l/KntWfdCHj6BdGNKFv570Qc+2Zxk/3CeHh/GWa+Vm9cp30CRL1hVdrV1wYckOR7TC5HCnq9zpHSMMrfBhVmp3WaeqdXdQ2jmj99IdJ6lo8w1pnp16F1jKa03f6vYF4t9k8NFp70RKpCjeV3Ckg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785689622; c=relaxed/simple; bh=ByRlyVHFPCd/MT9yGEpmiFRC7J42flCljkyyivYuqV8=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=bIsyOp3c5mXUU0cqSOv1fTmLUHFzDuHiLL0hyXkCLGQRSoE4WkOazzfzaPX7ZUrlPvSDjlpAGkvT0gXJGV9d22UR0zW7/8KM0dxZZ4CM69jA7+LkWTjBCJzsXkU2PA3OyYLj/HAeXmbBvV/QlXQss8deAHyXn6aqYwydyfF5zpo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bm/rX2Fe; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bm/rX2Fe" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3AACA1F00A3D; Sun, 2 Aug 2026 16:53:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785689621; bh=j+cZ37TDJBMZ9L167vXN8x67B74o3YUUPAA7LEgjGp0=; h=From:To:Cc:Subject:Date; b=bm/rX2FeQ8cnaJx/sM6cwOuREMnd3mBcGuLu7xUnvxAq2ia/ZmZWDRXJcRswHZn5W erJFxBZ0k+U7wJlqfTMTvDvYslyMUe0JQQHUow929tkYK8X9272cfErHRyiZ6A0v+U bberUa2JiLdBibcO5FqrbjFaTMlKW3kyWVzdMDQxNzxcj18pFaBMxsQofy3ZLft/7w ZMLeqiSrcMcJnnwUIMpgzO7QAzD0c0iyoI77+loQgEThLZUizITUOkUVOKM76jfoSU BPks4YbMYKfkfFWsDLnI2RCCZRqR1K8tCgLruEtNBxQ8pJwMbW4D0zrCz4kMEfmR3f LYk8LwyX3wO1g== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wqZRS-0000000BVIZ-2wd1; Sun, 02 Aug 2026 16:53:38 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Thomas Gleixner , Ben Horgan , Daniel Lezcano Subject: [PATCH v3 0/8] arm64: arch_timer: Improve errata handling Date: Sun, 2 Aug 2026 17:53:19 +0100 Message-ID: <20260802165327.385217-1-maz@kernel.org> X-Mailer: git-send-email 2.47.3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, tglx@kernel.org, ben.horgan@arm.com, daniel.lezcano@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false This is the third version of this series addressing a couple of embarrassing bugs in the prolific arm64 timer errata handling department. See below for the changes since v2. Time is hard. Timers are harder. As a consequence, we have plenty of broken counter/timer implementations in the wild, and an infrastructure to deal with them. However, what we have today suffers from a number of issues: - if, on an heterogeneous system, affected CPUs are secondaries, we do record their broken state but don't correct anything - we always play games with preemption in order to access per-CPU state, irrespective of the presence of broken CPUs I hear someone saying "just use a static key to enable the errata and be done with it". Good call, except that we need to do that from a CPUHP callback, and that's deadlock central. We can't do it later, because this could affect the CPU before the workaround is enabled. However, not everything is lost if we turn the logic on its head: - always start with the mitigations enabled, even if we don't know of any affected CPU - once all CPUs have been seen once, and that we still haven't enabled any workaround, disable the mitigations globally. With that, a normal kernel boot with all CPUs will quickly switch to no mitigation on decent HW. If you're booting with CPUs disabled, this will only kick in once you have booted them all. Patches on top of 7.2-rc4. * From v2 [1]: - Added a fix for the PMUv3 driver that really wants to know whether it is operating with the architected timer. This has been broken for some time (since 24ee7607b286b ("arm64/arch_timer: Provide noinstr sched_clock_read() functions")) - Make arch_timer_read_counter a function, and not just a function pointer - Added a command-line option to allow the user to promise that no erratum is required (Will) - Dropped the internal CPU mask and iterate over the existing per-cpu variable (Will) - Picked Catalin's Ack, with thanks [1] https://lore.kernel.org/all/20260508094203.2913880-1-maz@kernel.org/ Marc Zyngier (8): clocksource/drivers/arm_arch_timer: Add read_sched_clock_is_arch_counter() predicate clocksource/drivers/arm_arch_timer: Add a static key indicating the need for a runtime workaround clocksource/drivers/arm_arch_timer: Convert counter accessors to a static key alternative clocksource/drivers/arm_arch_timer: Drop the arch_counter_get_cnt{p,v}ct_stable() accessors clocksource/drivers/arm_arch_timer: Turn arch_timer_read_counter into a function clocksource/drivers/arm_arch_timer: Add command-line control over the counter errata management clocksource/drivers/arm_arch_timer: Expose a direct accessor for the virtual counter arm64: Convert __delay_cycles() to arch_timer_read_vcounter() .../admin-guide/kernel-parameters.txt | 13 ++ arch/arm64/lib/delay.c | 5 +- drivers/clocksource/arm_arch_timer.c | 156 ++++++++++++------ drivers/perf/arm_pmuv3.c | 2 +- include/clocksource/arm_arch_timer.h | 11 +- 5 files changed, 131 insertions(+), 56 deletions(-) -- 2.47.3