From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74CC03CAE80 for ; Sun, 2 Aug 2026 16:53:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785689624; cv=none; b=fi4uV4PGnPUIA/vvU6MrDlnZA/HThtNXkJ8fzYBa8LtLG1/XjYpqY8rQK2UsqAav7CwXR/COh5kXQ2a/UMYrKnAajuObNEC7TGidAqH8hdB4ayKQBx8EZntPHgGs3lFpINxijx1sHt2BNHW8jnnZYHowBnSjn3fzLFw9LTmePwI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785689624; c=relaxed/simple; bh=Dx2YA1KqlxtSazStCMOfdDCRKPW5jgznMF4uivzvqJA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UfKJ4JY/H1w5XXi+RExt3BS+LqsJ/ikH0+J5EcF2ULP5Ezn2D9T8mon/pCVoXwIq51hp7tHJFjd4jGkiSatsoykQ7yGki1CeMERQYynyL3m/Wr19/S3xsqoOaSWOElhok00N7oPmDq+ohTnciGgzhrXdENSpJYoeu0x9ex/qcic= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hZPwECgL; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hZPwECgL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5A7F11F00ACF; Sun, 2 Aug 2026 16:53:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785689622; bh=dEzw2i7HRKSDGO8dkn+XkGr8/pmxZoR0KreFTkdRu2g=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=hZPwECgLePdW81OBR1YR4NyrGRDDIKetg8utx56Gs5HhhCA9+DOL7gMeRG4i2U4mm ZNGmprY/crJiz0WWdjdjn78Mruk/vcbbGqyHJLo0JU8rf/jbWK07omNTXGI27b88mL KhZ/ASyNRc2DboxnoDIukeYNZMEOH/fxoxO0tNS4p+ZxXnARs4XOIuX/dxkOMh5ID+ 62b1KL9sh0Khy9z9Kh0PcG9v4WwvntCWcfGSVvZJdUcFP90+D1H/pjACczB4iGfohJ +l0FxFMYx5knd5ZIli4kKnqnqmC5D1TZzhoF2Bj/E60SgLd1BE9cwdnMQagP2sn8Xs FScbAHyg+UDoA== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wqZRU-0000000BVIZ-1kBi; Sun, 02 Aug 2026 16:53:40 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Thomas Gleixner , Ben Horgan , Daniel Lezcano Subject: [PATCH v3 4/8] clocksource/drivers/arm_arch_timer: Drop the arch_counter_get_cnt{p,v}ct_stable() accessors Date: Sun, 2 Aug 2026 17:53:23 +0100 Message-ID: <20260802165327.385217-5-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260802165327.385217-1-maz@kernel.org> References: <20260802165327.385217-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, tglx@kernel.org, ben.horgan@arm.com, daniel.lezcano@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Further simplify the counter accessors by eliminating the *_stable() ones, which serve little purpose at this stage. Signed-off-by: Marc Zyngier --- drivers/clocksource/arm_arch_timer.c | 38 +++++++++------------------- 1 file changed, 12 insertions(+), 26 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index f645aa562895b..5085e87706f99 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -100,19 +100,12 @@ static noinstr u64 raw_counter_get_cntpct(void) return __arch_counter_get_cntpct(); } -static notrace u64 arch_counter_get_cntpct_stable(void) +static notrace u64 arch_counter_get_cntpct(void) { - u64 val; - preempt_disable_notrace(); - val = __arch_counter_get_cntpct_stable(); - preempt_enable_notrace(); - return val; -} - -static noinstr u64 arch_counter_get_cntpct(void) -{ - if (arch_counter_broken_accessors()) - return arch_counter_get_cntpct_stable(); + if (arch_counter_broken_accessors()) { + guard(preempt_notrace)(); + return __arch_counter_get_cntpct_stable(); + } return __arch_counter_get_cntpct(); } @@ -125,19 +118,12 @@ static noinstr u64 raw_counter_get_cntvct(void) return __arch_counter_get_cntvct(); } -static notrace u64 arch_counter_get_cntvct_stable(void) +static notrace u64 arch_counter_get_cntvct(void) { - u64 val; - preempt_disable_notrace(); - val = __arch_counter_get_cntvct_stable(); - preempt_enable_notrace(); - return val; -} - -static noinstr u64 arch_counter_get_cntvct(void) -{ - if (arch_counter_broken_accessors()) - return arch_counter_get_cntvct_stable(); + if (arch_counter_broken_accessors()) { + guard(preempt_notrace)(); + return __arch_counter_get_cntvct_stable(); + } return __arch_counter_get_cntvct(); } @@ -342,10 +328,10 @@ void erratum_set_next_event_generic(const int access, unsigned long evt, ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; if (access == ARCH_TIMER_PHYS_ACCESS) { - cval = evt + arch_counter_get_cntpct_stable(); + cval = evt + arch_counter_get_cntpct(); write_sysreg(cval, cntp_cval_el0); } else { - cval = evt + arch_counter_get_cntvct_stable(); + cval = evt + arch_counter_get_cntvct(); write_sysreg(cval, cntv_cval_el0); } -- 2.47.3