From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3CC73CB2EA for ; Sun, 2 Aug 2026 16:53:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785689624; cv=none; b=faB4ddmj+EguDWjv0/d8zKlbEOAIGmW0/MquSDVNpzIM3WY/LITbGL8OQJMuSRquR1DL0Xlu0/t2jfiPUw25LCwGvyclyDpsYTDYgZpEKfMyKs4os+piMmwT6FqPbMmKmTEQCUh7mbUkDLCNi/7JSM5vAkr1jCd32nllsr4I5oo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785689624; c=relaxed/simple; bh=Ljr8Y8G4OWXk0i2OFlFuD9kNK/QO9C9ZOhFi5IaPU3M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RREmyADDNJ0ROlcXXGd7VrCZjxr3Sy7T5lv5tF0jGkBqMWlZbprPi19BaswbrnOvGDbtDD8COezG4/IYo9aAvuKYj7yJrA4fV98IeU8ZJe3axCrVeQyqDD0wAyXhJ7ibahwIMUYJ78eKtMzRKraAzJQPeOBM6Igt6/IC+MSZnyg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cH70UKcj; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cH70UKcj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AF14A1F00A3F; Sun, 2 Aug 2026 16:53:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785689622; bh=ZAAyG8SRRqbLdivjdRdMUZVSQc5/o7iuh79T8Z5zcL0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=cH70UKcj1v4XNHl3vPR/tf6CtySyuW6jNWyslMQYi1GJBQIchHJ7vBETdMqJgyZ/I Wb2gbUcmfVus5T4dxY/RPIhRYUMabZTyLqe+USI+B0jtuuLNmPy9X7qUuKX79W5D9S BOPRgGeTegqs/n6bK/VYETVWxHIj0v0J1djqLb06jVb7Vq3f+AUEaiLl0JJ7dMfCK/ ABwWpJNHYJHr+thOBAu697YxcOgnvo2VCegHdG7T4DtyjFal3xUDyfqCq431DRYipA KpddCi8wOiR55JfYAq1YaBWNqqPirGKxzk9zWZhRYJQAf2yxlz+lPON5+EZtZFO4V7 vfy+ALN9QQIoA== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wqZRU-0000000BVIZ-3eqS; Sun, 02 Aug 2026 16:53:41 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Thomas Gleixner , Ben Horgan , Daniel Lezcano Subject: [PATCH v3 5/8] clocksource/drivers/arm_arch_timer: Turn arch_timer_read_counter into a function Date: Sun, 2 Aug 2026 17:53:24 +0100 Message-ID: <20260802165327.385217-6-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260802165327.385217-1-maz@kernel.org> References: <20260802165327.385217-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, tglx@kernel.org, ben.horgan@arm.com, daniel.lezcano@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Now that we control the workarounds applied to the counters with a static key, we can also do the same thing for the selection between virtual and physical counters, as this selection is done on the boot CPU, where we have the freedom to flip static keys. With this, there is no need for arch_timer_read_counter to be a function pointer, and we can directly promote it to an actual function. While we're at it, apply the same static key treatment to the raw_* accessors. Signed-off-by: Marc Zyngier --- drivers/clocksource/arm_arch_timer.c | 38 +++++++++++++++++----------- include/clocksource/arm_arch_timer.h | 2 +- 2 files changed, 24 insertions(+), 16 deletions(-) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 5085e87706f99..747f51d9225c2 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -134,9 +134,21 @@ static notrace u64 arch_counter_get_cntvct(void) * to exist on arm64. arm doesn't use this before DT is probed so even * if we don't have the cp15 accessors we won't have a problem. */ -u64 (*arch_timer_read_counter)(void) __ro_after_init = arch_counter_get_cntvct; +static DEFINE_STATIC_KEY_TRUE(arch_counter_is_virtual); + +u64 notrace arch_timer_read_counter(void) +{ + return static_branch_likely(&arch_counter_is_virtual) ? + arch_counter_get_cntvct() : arch_counter_get_cntpct(); +} EXPORT_SYMBOL_GPL(arch_timer_read_counter); +static u64 noinstr raw_arch_timer_read_counter(void) +{ + return static_branch_likely(&arch_counter_is_virtual) ? + raw_counter_get_cntvct() : raw_counter_get_cntpct(); +} + static u64 arch_counter_read(struct clocksource *cs) { return arch_timer_read_counter(); @@ -940,22 +952,19 @@ struct arch_timer_kvm_info *arch_timer_get_kvm_info(void) static void __init arch_counter_register(void) { - u64 (*scr)(void); - u64 (*rd)(void); u64 start_count; int width; - if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) || - arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI || - arch_timer_uses_ppi == ARCH_TIMER_HYP_VIRT_PPI) { - rd = arch_counter_get_cntvct; - scr = raw_counter_get_cntvct; - } else { - rd = arch_counter_get_cntpct; - scr = raw_counter_get_cntpct; + switch (arch_timer_uses_ppi) { + case ARCH_TIMER_PHYS_SECURE_PPI: + case ARCH_TIMER_PHYS_NONSECURE_PPI: + case ARCH_TIMER_HYP_PPI: + static_branch_disable(&arch_counter_is_virtual); + break; + default: + break; } - arch_timer_read_counter = rd; clocksource_counter.vdso_clock_mode = vdso_default; width = arch_counter_get_width(); @@ -971,15 +980,14 @@ static void __init arch_counter_register(void) timecounter_init(&arch_timer_kvm_info.timecounter, &cyclecounter, start_count); - sched_clock_register(scr, width, arch_timer_rate); + sched_clock_register(raw_arch_timer_read_counter, width, arch_timer_rate); } bool read_sched_clock_is_arch_counter(const struct clock_read_data *crd) { u64 (*rd)(void) = crd->read_sched_clock; - return (rd == raw_counter_get_cntvct || - rd == raw_counter_get_cntpct); + return (rd == raw_arch_timer_read_counter); } static void arch_timer_stop(struct clock_event_device *clk) diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h index 84cdbaffcfb5e..8deb815ed0a08 100644 --- a/include/clocksource/arm_arch_timer.h +++ b/include/clocksource/arm_arch_timer.h @@ -89,7 +89,7 @@ struct clock_read_data; #ifdef CONFIG_ARM_ARCH_TIMER extern u32 arch_timer_get_rate(void); -extern u64 (*arch_timer_read_counter)(void); +extern u64 arch_timer_read_counter(void); extern struct arch_timer_kvm_info *arch_timer_get_kvm_info(void); extern bool arch_timer_evtstrm_available(void); extern bool read_sched_clock_is_arch_counter(const struct clock_read_data *); -- 2.47.3