From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D07663CC32D for ; Sun, 2 Aug 2026 16:53:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785689625; cv=none; b=FBiz5gXKTm83ngYL9uC4qThxZqaN3DLcGF5A4oC0F38AzXVTU/ATQREwUTc2D+o7dHRET3eJfOtcsSLzQ5GUFJ744Ig+BW0rjxXq//FkMoswY9W1kdxuu73XpQxB/YkIZv/8Q4oAjUXqoduexYyLIpP6vyISCVxs5q5GiEepYDA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785689625; c=relaxed/simple; bh=H0L3w+o6UadGsjx3EfHoFmROp0sOs/Nw64D6PDQZPs4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LlVBIAJyKQS8QlrzMEzWzLGMq7XHly6smPscGv1MUSOWh8DLEWHET7ztA2XLqmVQnfoUTNePfDYiO+DIYaZU+lGG6KzKTms3n31nWGAm2p+U4qlFbpoxVW9epOIAZIkqg/6u61U2pVP/WKiotQiSoql7Dv/5dFALPorPHFD776U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HWqIds1J; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HWqIds1J" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B3B461F01559; Sun, 2 Aug 2026 16:53:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785689623; bh=IPrlliaNT6d54S3Oz/pAE+1e1wLs+2Mvnn7Uhn7fUaM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=HWqIds1JtqxoC+GXg+J61Hb/rl+q23KepnybmBwzwlbJW9acaz/wb0XEcS1Tmz7Ul Sw6zLP7QaMh53864joQB3Tk+CLRt+l+qa3d4mqwaNt9QK7OYaQLDH/Hlwa59wXSOh4 qQ8XAocO5+86eR3C7qHx7O8XsbOtZvgJ2AEfpWvFwF5HxCCo9Vfsn+gdmh+Vf3fADg bz3BPlgm5YbLrkJZ3H0M1f6OeN8yr7e8PnO0Y8ZE62T44TS3g2i7RAt2w3+r0mp8bo WTQJpfIGyvIaRbF7P8swq164KxT6zVmPq73/rdXigAmcK0FWRBovF+a4o1WlKEfeJv 22yp6tbStDCgQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wqZRV-0000000BVIZ-3G7g; Sun, 02 Aug 2026 16:53:42 +0000 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Catalin Marinas , Will Deacon , Mark Rutland , Thomas Gleixner , Ben Horgan , Daniel Lezcano Subject: [PATCH v3 7/8] clocksource/drivers/arm_arch_timer: Expose a direct accessor for the virtual counter Date: Sun, 2 Aug 2026 17:53:26 +0100 Message-ID: <20260802165327.385217-8-maz@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260802165327.385217-1-maz@kernel.org> References: <20260802165327.385217-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, tglx@kernel.org, ben.horgan@arm.com, daniel.lezcano@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false We allow access to the architected counter via arch_timer_read_counter(). However, this accessor can either be the virtual or the physical view of the counter, depending on how the kernel has been booted. At the same time, we have some architectural features (such as WFIT, WFET) that rely on the virtual counter, and nothing else. If implementations were perfect, we'd rely on reading CNTVCT_EL0, and be done with it. However, we have a bunch of broken implementations in the wild, which rely on preemption being disabled and other costly workarounds. In order to provide decent performance on non-broken HW while still supporting the legacy horrors, expose arch_timer_read_vcounter() as a new helper that hides this complexity. Obviously, this is simply a global alias of arch_counter_get_cntvct(). Signed-off-by: Marc Zyngier --- drivers/clocksource/arm_arch_timer.c | 2 ++ include/clocksource/arm_arch_timer.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index b3b31d4f4815f..9c7501ce57073 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -128,6 +128,8 @@ static notrace u64 arch_counter_get_cntvct(void) return __arch_counter_get_cntvct(); } +u64 arch_timer_read_vcounter(void) __attribute__((alias("arch_counter_get_cntvct"))); + /* * Default to cp15 based access because arm64 uses this function for * sched_clock() before DT is probed and the cp15 method is guaranteed diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h index 8deb815ed0a08..32fd531ac009f 100644 --- a/include/clocksource/arm_arch_timer.h +++ b/include/clocksource/arm_arch_timer.h @@ -90,6 +90,7 @@ struct clock_read_data; extern u32 arch_timer_get_rate(void); extern u64 arch_timer_read_counter(void); +extern u64 arch_timer_read_vcounter(void); extern struct arch_timer_kvm_info *arch_timer_get_kvm_info(void); extern bool arch_timer_evtstrm_available(void); extern bool read_sched_clock_is_arch_counter(const struct clock_read_data *); -- 2.47.3