From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qk1-f177.google.com (mail-qk1-f177.google.com [209.85.222.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B945D233704 for ; Sun, 2 Aug 2026 21:35:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.222.177 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785706559; cv=none; b=k8c/qRM3JIO786qdcO68sz8p30Xli5X1UuxL/u98T4WrGWhvWUcW1X8gehgtv082zeva9gIXZdX6wWd5lkOfUAXmRphM0LWCWHyHXGhGnsGqO1sZ02YrKw6Wh8d8DW+s8p/+ztahRqLerymvR+NPAcpWps9KddsAVrHWdTQiAlA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785706559; c=relaxed/simple; bh=ClPmggE1H2hDxAIazFG6cTNl0MH4zKn5rOcL2jW356o=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=kKbrzjzzhPosFSA+4Km3JtTcSkgSiC6bZ3c9KRN5OhLUztPnil+s32VEZAQOZGY2IStrYsASo9jFiOfI05PcTo+DwzkncTTA3oEdLHrogpCWgduXA6/7/77ySEfJGmpmKUABRCaH8WCRf0FhTBQYxgvkQR8nTLLcTkbe/G0sWzk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=bowXbmTr; arc=none smtp.client-ip=209.85.222.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bowXbmTr" Received: by mail-qk1-f177.google.com with SMTP id af79cd13be357-92e57a753f9so205535985a.2 for ; Sun, 02 Aug 2026 14:35:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1785706556; x=1786311356; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to:content-type; bh=IMLCThtFbty884Ww5GsR0VERFJXBrTfQZvrEMr+iO/Y=; b=bowXbmTr49WvsJlyN08ehEzrOyRUeXn1G/ahcQit4pnDnhfquHZHF9XkdEJh50ZPWC luHGoHCX0oR4mt+OImsicwTrTxM0immK3SmfO79Onq8A+6YJbFRyLiSfGvG0LmfZKOYL F0cFY3NDvra+XrZmimjk17QobYKA/+GWFWN0gXuCU3htpOOffqQYnWBBMb7cFgvaaPFU 0bx5DXxWuFokTIGbiK9MhUmYLPZTiaq/umtZjazQS1l/9P+WkaT0XNs9ACZRbzv+9lir UpDFQFTLO17DIZkVSTSWTp6cUzJkEm5wHZdXg9Q3Eg+G0qsDjGejdCM3xOpEH+ndjndg qOQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1785706556; x=1786311356; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to:content-type; bh=IMLCThtFbty884Ww5GsR0VERFJXBrTfQZvrEMr+iO/Y=; b=gAZ6lSz8ZQhCQ2yH8jvLR0y4MDdf+D5a2G09b0WFE4HfgAUTqGFKlgarO0NiwGQUCL +LWV4ioEhBfrP6IlvrJ5h++bVZCes22CXcSD2jrEE78k50JUM9aW45jUy7+pFRZXFA2k R5M70g/qkzCktXeCT5xuEjICtA83d+WVSEsABKoZHV2DIrj1ePTsMDWRAn2KF7UoAMte JlhsfAUvyBIC/VEoX+U6CkR0CeHQJB5/6rCoW7venhwGVqsj5nAQ/0L3kAPPv+aXBMIp Icr+LEnFOYk76IkD+08kSRv0Wcw3auEhsid9TibT5jp1Uos2sUkefuBBpnVMFZQmzZXx fVGw== X-Forwarded-Encrypted: i=1; AHgh+Rpo9KIyLgLDgeoDCDCvl9+FqJnHX+6kUffuYt4zf+M8+lSGSipjBn7TbDgGuEs0XyuYwgOj4UWv9XTE4C8=@vger.kernel.org X-Gm-Message-State: AOJu0YwzYHYU+rTWt6iKTdMw3aCJ1igUYMA+SVWMuDyjFGzGx93Rvqqa Y+odmnSnvAHrrR6mfkf3f2+7pDZbOV0T70kPeAq5ljZPtVOqWL8rageo X-Gm-Gg: AR+sD11XnsnyqjM+R1WMa52seHho93wD6QgTgmBPCf69iAQHB5rm1k2Qqpltt9cRwRm 9wKc2oorMdYx/8ryv55VBs6rnPkYh7ZR0V7VzJGKyX7v967HAhSJHUTk56M0v7q+h4VOr5yfIkY 2dmw8whkt3sbGXEePLyoU1zDHp60ivyJMEnOo3DO3yABcPbfyTlIIXh1teIUFf61JY7Mh5bKZWZ aFSM6jVuI/lqoyoibwCzyIUc1989qa1y2uRRX8anCt88KSumA9CroxLj+kQUBbvKkJDcfmUakQF mEW5lbAzbd68HN50EN9d2zyCCWIP03AdOeu9FAukDiiCPYOd7PWapn41NHy9IjNbeKWAmRq/Vhk qa7mxKt1UVhNIfwVsd4n5Ggi6rb/BTAJ9BCjC9vyGy0Tj9/YSGntKgbt+0WgIsC5axu3K6JjwHm oh3EBHaUI+MThiPB2A2L4nTIkH8A3b6eG/S+2S7ojn43nXSLO27aAlew5I63Rr3jGQjMH8EB0yC plv5i/vwmg3SaVZP6DgA1BLJwqP8W/iFtGnZwmpPQtXVQk6J+VEpDOV4CztgOM= X-Received: by 2002:a05:620a:72c3:20b0:92e:675e:8eef with SMTP id af79cd13be357-934a078e724mr1118003285a.15.1785706556527; Sun, 02 Aug 2026 14:35:56 -0700 (PDT) Received: from i4-gl-tmk5904.ad.psu.edu ([130.203.156.186]) by smtp.gmail.com with ESMTPSA id af79cd13be357-9349c1c8816sm525615685a.36.2026.08.02.14.35.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Aug 2026 14:35:55 -0700 (PDT) From: Yuho Choi To: daniel.lezcano@kernel.org Cc: tglx@kernel.org, linux-kernel@vger.kernel.org, Yuho Choi Subject: [PATCH v1] clocksource: armada: Unwind timer clock on init failure Date: Sun, 2 Aug 2026 17:35:45 -0400 Message-ID: <20260802213545.565913-1-dbgh9129@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Armada timer init paths enable their clock before calling the common initialization routine. If that routine returns an error, the clock is left enabled even though the timer was not initialized successfully. Fixes: 12549e27c63c ("clocksource/drivers/time-armada-370-xp: Convert init function to return error") Signed-off-by: Yuho Choi --- drivers/clocksource/timer-armada-370-xp.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/timer-armada-370-xp.c b/drivers/clocksource/timer-armada-370-xp.c index a405a084cf72..b5a984aa1cbb 100644 --- a/drivers/clocksource/timer-armada-370-xp.c +++ b/drivers/clocksource/timer-armada-370-xp.c @@ -349,7 +349,11 @@ static int __init armada_xp_timer_init(struct device_node *np) timer_clk = clk_get_rate(clk); - return armada_370_xp_timer_common_init(np); + ret = armada_370_xp_timer_common_init(np); + if (ret) + clk_disable_unprepare(clk); + + return ret; } TIMER_OF_DECLARE(armada_xp, "marvell,armada-xp-timer", armada_xp_timer_init); @@ -387,7 +391,11 @@ static int __init armada_375_timer_init(struct device_node *np) timer25Mhz = false; } - return armada_370_xp_timer_common_init(np); + ret = armada_370_xp_timer_common_init(np); + if (ret) + clk_disable_unprepare(clk); + + return ret; } TIMER_OF_DECLARE(armada_375, "marvell,armada-375-timer", armada_375_timer_init); @@ -410,7 +418,11 @@ static int __init armada_370_timer_init(struct device_node *np) timer_clk = clk_get_rate(clk) / TIMER_DIVIDER; timer25Mhz = false; - return armada_370_xp_timer_common_init(np); + ret = armada_370_xp_timer_common_init(np); + if (ret) + clk_disable_unprepare(clk); + + return ret; } TIMER_OF_DECLARE(armada_370, "marvell,armada-370-timer", armada_370_timer_init); -- 2.43.0