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(unknown [10.28.34.91]) by maili.marvell.com (Postfix) with ESMTP id 3FDAD5B6939; Mon, 3 Aug 2026 21:18:45 -0700 (PDT) From: Umesh Kumar To: Mika Westerberg , Andi Shyti CC: Andy Shevchenko , , , , Umesh Kumar Subject: [RFC PATCH] i2c: designware: Enable SAR in slave mode for Multiple SAR controllers Date: Tue, 4 Aug 2026 09:48:42 +0530 Message-ID: <20260804041842.3205356-1-ukumar@marvell.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: _BOeKOviEK9ecxMWzhUWtDNWPjscyowm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA0MDAzMCBTYWx0ZWRfXxdufCXTuMdkj nkoGmiv2GwP/Fz7KpMBWn8joUn1TW9OCm3GC9XaI0VChmtWG/r+v9BbPwKbORklyMjpeR2v2VDg lUXuNRwvLa6GUr6Dhk23pZj3NWauZ+UpsLku8ODMCrCHzVVN1en4aUSwzuXtIVgIvPr1YwoRKMc vn5T1tCP9BQf1LTHck5seOEhnPgnBR7OzK2E60jSMshUm/EGMk3BwsIYXdrBFOmeAuehZCt2Dfl c82xtT4HKa1tVWo0Ahq4IhoWxdQA0byCrrd3zR2o2RaP4++xYWR1gcxGPZ2LhFH+hKpPcC6TM82 6f5HGE7UuqIs+g0DCiHx1n7meWYTdD8luIr18uqKfgS2y8dyOfY3WcYqMNB1zFxrmHqD1BlaeRA /OHpEqKucgCPwN6HVxd9pCxtJt8dRN04b3KCh/rwF0d/u/IYIJzd+ieAyw0KSETezAiIqiIMePw yq5c0kw3ni3kTJR37qw== X-Proofpoint-Spam-Info: AW1haW4tMjYwODA0MDAzMCBTYWx0ZWRfX+zjowILU4Qkg DcO9H8sUVHO9VIGzKsmnPzQOd1wd5wd9ZRDqTkp8lWo7AVzhzJ5Jm4IchgS6GxfYNcD7/OrP58P gdgdVe2ACdINQK37+O4jBMDlIje8pNc= X-Proofpoint-ORIG-GUID: _BOeKOviEK9ecxMWzhUWtDNWPjscyowm X-Authority-Analysis: v=2.4 cv=TPx1jVla c=1 sm=1 tr=0 ts=6a716829 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=qit2iCtTFQkLgVSMPQTB:22 a=M5GUcnROAAAA:8 a=gLBk0peu4sbVRRmL7qUA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-04_01,2026-08-03_02,2025-10-01_01 DesignWare controllers synthesised with the Multiple SAR feature (e.g. Marvell CN20K) only acknowledge traffic to the primary slave address (IC_SAR) when IC_ENABLE[19] (SAR_EN) is set. The slave enable path writes only IC_ENABLE[0], so on such controllers the target never ACKs its address and a remote master cannot reach it. Set SAR_EN together with ENABLE when entering slave mode. The bit is reserved (and ignored) on single-SAR controllers, so existing users are unaffected. Signed-off-by: Umesh Kumar --- RFC note: On our multi-SAR CN20K the slave only ACKs with IC_ENABLE[19] set. Existing single-SAR users work without it, and the bit is reserved there, so I've written it unconditionally. Would you prefer this gated behind a per-device capability flag instead? The CN20K PCI device enablement (which would set such a flag) can follow as a separate series. drivers/i2c/busses/i2c-designware-common.c | 9 ++++++++- drivers/i2c/busses/i2c-designware-core.h | 6 ++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c index 4dc57fd56170..b6f3d71cf268 100644 --- a/drivers/i2c/busses/i2c-designware-common.c +++ b/drivers/i2c/busses/i2c-designware-common.c @@ -374,7 +374,14 @@ static void i2c_dw_configure_mode(struct dw_i2c_dev *dev, int mode) regmap_write(dev->map, DW_IC_CON, dev->slave_cfg); regmap_write(dev->map, DW_IC_SAR, dev->slave->addr); regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_SLAVE_MASK); - __i2c_dw_enable(dev); + /* + * Controllers synthesised with the Multiple SAR feature only + * acknowledge traffic to IC_SAR when SAR_EN is set; a plain + * enable is not enough. The bit is reserved (ignored) on + * single-SAR controllers. + */ + regmap_write(dev->map, DW_IC_ENABLE, + DW_IC_ENABLE_ENABLE | DW_IC_ENABLE_SAR_EN); break; default: WARN(1, "Invalid mode %d\n", mode); diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h index 9d8d104cc391..35eaf2d7404f 100644 --- a/drivers/i2c/busses/i2c-designware-core.h +++ b/drivers/i2c/busses/i2c-designware-core.h @@ -125,6 +125,12 @@ #define DW_IC_ENABLE_ENABLE BIT(0) #define DW_IC_ENABLE_ABORT BIT(1) +/* + * On controllers synthesised with the Multiple SAR feature (e.g. Marvell + * CN20K), the primary slave address register (IC_SAR) only acknowledges bus + * traffic when this bit is set. It is reserved on single-SAR controllers. + */ +#define DW_IC_ENABLE_SAR_EN BIT(19) #define DW_IC_STATUS_ACTIVITY BIT(0) #define DW_IC_STATUS_TFE BIT(2) -- 2.43.0