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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47febfdd383sm7437135f8f.8.2026.08.05.04.10.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Aug 2026 04:10:41 -0700 (PDT) Date: Wed, 5 Aug 2026 12:10:39 +0100 From: David Laight To: "David Hildenbrand (Arm)" Cc: "Christoph Lameter (Ampere)" , "Lorenzo Stoakes (ARM)" , Mark Rutland , Yang Shi , Ryan Roberts , dennis@kernel.org, tj@kernel.org, urezki@gmail.com, catalin.marinas@arm.com, will@kernel.org, akpm@linux-foundation.org, hca@linux.ibm.com, gor@linux.ibm.com, agordeev@linux.ibm.com, linux-mm@kvack.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linus Torvalds , Jason Gunthorpe Subject: Re: [RFC v2 PATCH 0/16] Optimize this_cpu_*() ops for non-x86 (ARM64 for this series) Message-ID: <20260805121039.471c7340@pumpkin> In-Reply-To: <84b31836-1d10-4bec-a469-468b91fd4645@kernel.org> References: <20260715180455.515692-1-yang@os.amperecomputing.com> <0344c559-1959-4531-9265-d5a5180eb7cd@arm.com> <25d1e09b-53e4-7cd5-87db-b58437e4e690@gentwo.org> <4887267b-dc26-4c33-96ca-8dff054a0d1f@kernel.org> <63ea8156-a109-b2a2-6d35-1c17ad7f1a9d@gentwo.org> <84b31836-1d10-4bec-a469-468b91fd4645@kernel.org> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Tue, 4 Aug 2026 18:47:26 +0200 "David Hildenbrand (Arm)" wrote: > On 8/4/26 18:19, Christoph Lameter (Ampere) wrote: > > On Tue, 4 Aug 2026, Lorenzo Stoakes (ARM) wrote: > > > >> Since this work seems to be very much arm64-focused, perhaps it's therefore > >> worth looking at an alterative solution that's specific to the arch, like the > >> one suggested by Mark ([1])? > >> > >> [0]:https://lore.kernel.org/all/CAHk-=wire3dzhHx=KiL_f5Rj0=1u9ustsa33QoR-F9-v-NU9Ng@mail.gmail.com/ > >> [1]:https://lore.kernel.org/linux-arm-kernel/al_DpFJFcmVhxpvW@J2N7QTR9R3/ > > > > Mark's solution does replace the preempt_enable/disable sections with a > > rather hacky restart logic. It relies on a long preemable and postscript > > to each per cpu operations. > > Okay, so 3 simple instructions of preemable is "long preemable"? In which universe? > > But I am sure you did you homework and have data to back up your claims. Please > share that data, because I am very curious. The proposed sequence is: > // Prologue. Enable fixups for and . > 1 mrs , sp_el0 > 2 mov , #__VAL_PCPU_GPRS(, , ) > 3 strh , [, #TSK_TI_PCPU_GPRS] > > // Generate cpu-specific address > 4 mrs , TPIDR_ELx > 5 add , , > > // Perform access sequence > 6 ldr , [] > > // Epilogue. Disable fixups > 7 strh wzr, [, #TSK_TI_PCPU_GPRS] Think about how that actually gets execute by a real cpu. Instructions will be read from the I-cache in 'chunks' (maybe half a cache line). They are then fed to multiple decoders that generate u-ops for the execution units. The decoder is unlikely to be a bottleneck. I've numbered the instructions: First clock can run instructions 1, 2 and 4. Assuming the mrs have no extra latency the second runs 3 and 5. The third will then run 6 and 7. The cpu then probably has to wait for the result of the ldr. If the access is a write then there may be a stall waiting for the value to be written to be available. The only real effect of the extra instructions is likely to be code size. David