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[2a00:1028:83b8:1e7a:3010:3bd6:8521:caf1]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47ff7b250cfsm7334699f8f.28.2026.08.06.08.44.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 08:44:12 -0700 (PDT) Date: Thu, 6 Aug 2026 17:44:08 +0200 From: Petr Tesarik To: Sandipan Das Cc: , , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , "Alexander Shishkin" , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Thomas Gleixner , Borislav Petkov , Dave Hansen , , "H . Peter Anvin" , Ravi Bangoria , Ananth Narayan Subject: Re: [PATCH 3/3] perf/x86/amd: Implement x86_pmu::print_debug Message-ID: <20260806174408.37b8e232@mordecai> In-Reply-To: References: X-Mailer: Claws Mail 4.4.0 (GTK 3.24.52; x86_64-suse-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Thu, 6 Aug 2026 15:33:28 +0530 Sandipan Das wrote: > Implement x86_pmu::print_debug for PerfMonV2 capable processors to dump > MSR_AMD64_PERF_CNTR_GLOBAL_{CTL,STATUS}, plus MSR_AMD_DBG_EXTN_CFG if > LBR Extension Version 2 is available. Chain into x86_pmu_print_debug() > afterwards to dump the event selectors and counters. > > MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_{CLR,SET} are left out since they are > write-only. > > Fixes: 21d59e3e2c40 ("perf/x86/amd/core: Detect PerfMonV2 support") > Reported-by: Petr Tesarik > Closes: https://lore.kernel.org/all/20260717150315.2868314-1-ptesarik@suse.com/ > Cc: stable@vger.kernel.org > Signed-off-by: Sandipan Das This works great on my system, no more unchecked MSR access errors, and the logged values look correct. Feel free to add Tested-by: Petr Tesarik Thank you! Petr T > --- > arch/x86/events/amd/core.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c > index a787409f5a62..ecd648af81f7 100644 > --- a/arch/x86/events/amd/core.c > +++ b/arch/x86/events/amd/core.c > @@ -841,6 +841,25 @@ static void amd_pmu_v2_disable_all(void) > amd_pmu_check_overflow(); > } > > +static void amd_pmu_v2_print_debug(int cpu) > +{ > + u64 ctrl, status, debugextn; > + > + rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_CTL, ctrl); > + rdmsrq(MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, status); > + > + pr_info("\n"); > + pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); > + pr_info("CPU#%d: status: %016llx\n", cpu, status); > + > + if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_V2)) { > + rdmsrq(MSR_AMD_DBG_EXTN_CFG, debugextn); > + pr_info("CPU#%d: debugextn: %016llx\n", cpu, debugextn); > + } > + > + x86_pmu_print_debug(cpu); > +} > + > DEFINE_STATIC_CALL_NULL(amd_pmu_branch_add, *x86_pmu.add); > > static void amd_pmu_add_event(struct perf_event *event) > @@ -1452,6 +1471,7 @@ static int __init amd_core_pmu_init(void) > x86_pmu.disable_all = amd_pmu_v2_disable_all; > x86_pmu.enable = amd_pmu_v2_enable_event; > x86_pmu.handle_irq = amd_pmu_v2_handle_irq; > + x86_pmu.print_debug = amd_pmu_v2_print_debug; > static_call_update(amd_pmu_test_overflow, amd_pmu_test_overflow_status); > } >