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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?L6U5wEkaT2vX3WDJlkDQ86j2OXErpoYAkiWH5ss7QIq5Smsai/xYND+3Y/sq?= =?us-ascii?Q?stbjD/DnQzJuqK7ViEqdOhpQvexWlb/s+r34DG04YvNWzxHS0MIB4VAXcvdJ?= =?us-ascii?Q?rF8We87sOjYkhBTg3izQ6AGqALnYlIFl2sLdHpkmhtP2E2c0zdxeG967lgar?= =?us-ascii?Q?8H+P3235MJFRUhLRljJaqCTIxEtIsCZ4rS4auSMNZA07eECN9VCp2EIjy8p7?= =?us-ascii?Q?lr3WcbH0Qzp3mYm21Cd/CHh3zPmCdFfM6vPQKEDhG7lj6jC/Nx39ZyhoSmvB?= =?us-ascii?Q?4Idj12MUzni83FM1VlwK6/x9sucemrS4o0KxYXEAa2y452uDqAt/XsRE7o7j?= =?us-ascii?Q?LDdPkG/csNFUwDiBB4DMzfbGeITEgDsvMRD/YwZBMJMpVBnw/4QVKdXKwfzA?= =?us-ascii?Q?9w8MBYoNXjSHrugwmjsdneCzrt5rJHSX8GwIB33SWjH7YGn+of4NWptAMlha?= =?us-ascii?Q?RsugcJMF4RPA4AyA7wGtwpgOmmZZKcBGOsJIwrS/WNhgaxuiPSpo1CJijboz?= =?us-ascii?Q?8mk5VlSvHIhaoFoqzLAruMAIaYlWclc4SI8lA2k5Xq7JdoSgzoK9fB6Hb6nU?= =?us-ascii?Q?gj88a45cvLEKqrncRWOS6RtWcMTzUcE79uNZj4ySlzfV8wwROZT3ofKH1tjk?= =?us-ascii?Q?wUlsGn5jEU8tBoJnOzb45orc4AlaX88wZKbHzp3QbtznAXEDmPKJ04fl+93B?= =?us-ascii?Q?6eyYZyULJ9AN/fCurn7R7BEUsFzt+8UV4VOKmBydObIgkwib/WGGziL0Q+/i?= =?us-ascii?Q?DcZ8chOHsMvVwDamAZyUyAMgxAc5FnyG4IJFWER5tQJvvqEhJDoz83lbsr6e?= =?us-ascii?Q?a9D9WjDwwbNmR9N3ZZ/aqEtrSt8zDHXYm2Av9qg6pzQkkrhY5LdyxOZ6UV8Q?= =?us-ascii?Q?He4ke3hLpSOHe7dYLofWxGB3CAI1h2LrKcAKjATmvq/WIsnUt+YoY+rrp6gJ?= =?us-ascii?Q?pvZt7fjcBvGQmJ95ElcAsDAeMINd6RiV8Jl7bosPiro9T+uIJl2lCaQV8pjt?= =?us-ascii?Q?IvnqsY/A5Lq+oB848MvWdCqFUvRDBLLCSqJlW7mXsTVYC4jVPGgzxSC8O1eP?= =?us-ascii?Q?T+H01iTpB3eLdQO0yQ6ej7jVCj2KSxKLwGdyI2Up61kt5gvn5ZUi1JL+abHw?= =?us-ascii?Q?AeA8Bj10LWT21Vu7/sv/WcRcgawSFTf4/E+2/+n9EUygDD8+4s/WV20QeoOm?= =?us-ascii?Q?WlwcfsSjoIxKrc161ZUz/c0MO3NQCFLKzH/ZRkGtIr8EOShiGe8p+kExjdCW?= =?us-ascii?Q?PU0GYekvL46FEu7Nu5XTSEW2ymc2Qvq9wKQhj91jPZcvl3QmTbULGM06InoR?= =?us-ascii?Q?eGLotQgWQBsxbuFic32tT2x6GAN4LU1PwPYwQa7seuwmm+Yl0LuJn0mvRa7m?= =?us-ascii?Q?fQxDPj7i6/ROHp8OPFsYCP3DpD3CMW5XOA5zno1RgwOo1AmPNFTQG1nF2dI7?= =?us-ascii?Q?cWoKDOmlhKq+NEWcwMtX4jQ2AsXvV3xC44f+ktRnllZNjyk+R+ZhdKwZg9KU?= =?us-ascii?Q?C/bIpKsgwP4d8H7SZmakAP33z7LeYY3BSDKFMFzH8rrg4jXm11qTdygmOWA9?= =?us-ascii?Q?VVqpVDzZrIMxFxNnEyegfc0S0s3GxMNiSEbuDc8MoA6JQV58xWFejRlSqqbH?= =?us-ascii?Q?okuJoddVZLyj/GNi2pO1usqrrXqQcY0yJCzkSXR+jWSw1K8gT1IvvwVvWeaF?= =?us-ascii?Q?XHs63oPp7Zo8hNWzJSUkfZycGJ6S1NEkmbm3aRY9bCmuofrogjhtPnIJiPR9?= =?us-ascii?Q?zcwxWrZ9fg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 560c0f79-8c1c-4d7f-2859-08def4fabe39 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2026 03:11:30.5239 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 5ALE3kIuTn15++ah2o7AlcTteoShRD3GgjO38VUkjGfxd7cv60VT0xi4qAsnBJa7RwuRKmXJIp43K6ROUoIwUg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4198 GIN, the GPU Interrupt and Notification unit, is the GPU's interrupt controller. Each PCIe function has its own tree, whose leaf count depends on the GPU family. Message-signaled delivery stops after each edge until the CPU rearms it, and the rearm write differs by family and interrupt type: * Pre-Hopper MSI writes an EOI through the BAR0 PCI configuration space mirror. * MSI for Hopper and later cycles the TOP enable bits of every serviced subtree. * MSI-X on any family cycles the bits of the handler's own subtree. Provide the leaf count and the rearm method through a per-architecture interrupt HAL. Assisted-by: Cursor:claude-opus-5 Reviewed-by: Will Pierce Signed-off-by: John Hubbard --- drivers/gpu/nova-core/irq.rs | 12 ++- drivers/gpu/nova-core/irq/hal.rs | 113 +++++++++++++++++++++++++ drivers/gpu/nova-core/irq/hal/gh100.rs | 30 +++++++ drivers/gpu/nova-core/irq/hal/tu102.rs | 29 +++++++ 4 files changed, 182 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/nova-core/irq/hal.rs create mode 100644 drivers/gpu/nova-core/irq/hal/gh100.rs create mode 100644 drivers/gpu/nova-core/irq/hal/tu102.rs diff --git a/drivers/gpu/nova-core/irq.rs b/drivers/gpu/nova-core/irq.rs index b70efc239334..ef77066e0514 100644 --- a/drivers/gpu/nova-core/irq.rs +++ b/drivers/gpu/nova-core/irq.rs @@ -1,6 +1,16 @@ // SPDX-License-Identifier: GPL-2.0 // SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +//! GPU interrupt support. +//! +//! GIN, the GPU Interrupt and Notification unit, is the GPU's interrupt controller: a two-level +//! tree of pending and enable registers, one tree per PCIe function. +//! +//! See `Documentation/gpu/nova/core/interrupts.rst`. + +mod hal; +mod interrupt_tree; + use kernel::{ device::Bound, pci::{ @@ -11,8 +21,6 @@ prelude::*, }; -mod interrupt_tree; - pub(crate) fn alloc_vector(pdev: &pci::Device) -> Result> { let msi_types = IrqTypes::default().with(IrqType::Msi).with(IrqType::MsiX); diff --git a/drivers/gpu/nova-core/irq/hal.rs b/drivers/gpu/nova-core/irq/hal.rs new file mode 100644 index 000000000000..8de2f6e536c2 --- /dev/null +++ b/drivers/gpu/nova-core/irq/hal.rs @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + +//! Per-architecture properties of the GIN CPU interrupt tree. + +mod gh100; +mod tu102; + +use kernel::{ + io::Io, + pci::IrqType, // +}; + +use crate::{ + driver::Bar0, + gpu::{ + Architecture, + Chipset, // + }, + regs, // +}; + +/// Register write that restores PCI interrupt delivery to the CPU. +/// +/// A message-signaled interrupt is delivered once per edge, and the PCI side delivers no further +/// interrupt until the CPU rearms it. A handler that returns without this write receives no more +/// interrupts. +#[derive(Clone, Copy, Debug, Eq, PartialEq)] +pub(super) enum PciIrqRearmMethod { + /// The MSI end-of-interrupt register in the BAR0 PCI configuration-space mirror, used by + /// MSI on pre-Hopper GPUs. + ConfigMirrorEoi, + + /// A clear then a set of the `TOP` enable bits of every serviced subtree, which produces the + /// edge that delivers the next interrupt. + /// + /// MSI has a single message that every subtree raises, so the rearm covers the whole serviced + /// set. + TopEnableCycleServiced, + + /// The same enable cycle, restricted to the one subtree the handler serves. + /// + /// MSI-X gives each subtree its own table entry and its own handler. + TopEnableCycleSubtree, +} + +impl PciIrqRearmMethod { + /// Performs this method's register write. + /// + /// `serviced` holds the `TOP` bit of every subtree the driver services, and `subtree` holds + /// the bit of the one subtree the calling handler serves. Each method uses whichever of the + /// two its interrupt type delivers on, so both are required. + #[expect(dead_code)] + pub(super) fn rearm(self, bar: Bar0<'_>, serviced: u32, subtree: u32) { + let subtrees = match self { + // The written value is ignored, so any write rearms delivery. + Self::ConfigMirrorEoi => { + bar.write(regs::tu102::NV_XVE_CYA_2, 0u32.into()); + return; + } + Self::TopEnableCycleServiced => serviced, + Self::TopEnableCycleSubtree => subtree, + }; + + bar.write( + regs::NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR, + subtrees.into(), + ); + bar.write( + regs::NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET, + subtrees.into(), + ); + } +} + +/// Per-architecture properties of the GIN CPU interrupt tree. +/// +/// The tree size and the method that rearms PCI interrupt delivery differ by family. The tree +/// walk, the vector encoding, and the read-and-clear sequence do not, and are in generic code. +/// +/// See `Documentation/gpu/nova/core/interrupts.rst`. +pub(super) trait CpuInterruptHal { + /// Returns the number of implemented interrupt leaves in the CPU tree. + /// + /// Each leaf is a 32-bit register, so the tree carries `num_leaves * 32` vectors. + fn num_leaves(&self) -> usize; + + /// Returns the subtrees this architecture implements. + /// + /// Each `TOP` bit covers two adjacent leaves, so the tree has `num_leaves / 2` subtrees and + /// the result has one bit set for each. Bits outside the result are not meaningful in + /// `TOP_EN_SET` or `TOP_EN_CLEAR`. + fn implemented_subtrees(&self) -> u32 { + (1u32 << (self.num_leaves() / 2)) - 1 + } + + /// Returns the method that rearms PCI interrupt delivery for `irq_type`. + /// + /// `None` means that `irq_type` needs no rearm write. That is the case for `INTx`, which is + /// level-triggered, and which nova-core does not allocate. + #[expect(dead_code)] + fn pci_irq_rearm_method(&self, irq_type: IrqType) -> Option; +} + +/// Returns the [`CpuInterruptHal`] for `chipset`. +pub(super) fn cpu_interrupt_hal(chipset: Chipset) -> &'static dyn CpuInterruptHal { + match chipset.arch() { + Architecture::Turing | Architecture::Ampere | Architecture::Ada => tu102::TU102_HAL, + Architecture::Hopper | Architecture::BlackwellGB10x | Architecture::BlackwellGB20x => { + gh100::GH100_HAL + } + } +} diff --git a/drivers/gpu/nova-core/irq/hal/gh100.rs b/drivers/gpu/nova-core/irq/hal/gh100.rs new file mode 100644 index 000000000000..69bd092e38b5 --- /dev/null +++ b/drivers/gpu/nova-core/irq/hal/gh100.rs @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + +use kernel::pci::IrqType; + +use super::{ + CpuInterruptHal, + PciIrqRearmMethod, // +}; + +/// GIN parameters for Hopper and Blackwell, which implement a 16-leaf CPU tree. Only 12 leaves +/// carry sources. +struct Gh100; + +impl CpuInterruptHal for Gh100 { + fn num_leaves(&self) -> usize { + 16 + } + + fn pci_irq_rearm_method(&self, irq_type: IrqType) -> Option { + match irq_type { + IrqType::Intx => None, + IrqType::Msi => Some(PciIrqRearmMethod::TopEnableCycleServiced), + IrqType::MsiX => Some(PciIrqRearmMethod::TopEnableCycleSubtree), + } + } +} + +const GH100: Gh100 = Gh100; +pub(super) const GH100_HAL: &dyn CpuInterruptHal = &GH100; diff --git a/drivers/gpu/nova-core/irq/hal/tu102.rs b/drivers/gpu/nova-core/irq/hal/tu102.rs new file mode 100644 index 000000000000..590f0dc9a701 --- /dev/null +++ b/drivers/gpu/nova-core/irq/hal/tu102.rs @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. + +use kernel::pci::IrqType; + +use super::{ + CpuInterruptHal, + PciIrqRearmMethod, // +}; + +/// GIN parameters for Turing, Ampere, and Ada, which implement an 8-leaf CPU tree. +struct Tu102; + +impl CpuInterruptHal for Tu102 { + fn num_leaves(&self) -> usize { + 8 + } + + fn pci_irq_rearm_method(&self, irq_type: IrqType) -> Option { + match irq_type { + IrqType::Intx => None, + IrqType::Msi => Some(PciIrqRearmMethod::ConfigMirrorEoi), + IrqType::MsiX => Some(PciIrqRearmMethod::TopEnableCycleSubtree), + } + } +} + +const TU102: Tu102 = Tu102; +pub(super) const TU102_HAL: &dyn CpuInterruptHal = &TU102; -- 2.55.0