From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D112526A1CF; Sun, 9 Aug 2026 13:15:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786281322; cv=none; b=llubU7hirfiysryaqhOUqNPm32/HCbYbhJD+3VCXN6mMy1D4VwB5tCSYU6q6/+XeTpmKol5t7uX/xTfRzW6nQunqbRs1fgbwHcQZlgYjHm5fMJZgpTkIiG+dbtggwvfaqhb2e8BFv+0tpSOoYpPpkdgUCj+Sno7gNN6VqtOTFck= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786281322; c=relaxed/simple; bh=GaC5ILihit460FZxqqZmeMPb77gx2K+GWLRT410+nv4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jAlxiNBBl6zFaGKb/Oh9yOW+TsDYv9aMxC8VssBoA2UWicrQtPMLwK5A8nw7elTjCLkdd2Cehr/YYuJR4vXMbrTM/joWBnDxLL8BONHIHAqzKM5VQ6kCvepyZfUM7AuQiMDKaUDqL4GRXzxS6meFa/vnaOo0D3GJeeQHBlhtMT0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GcIXoyPp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GcIXoyPp" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4E136C2BCF6; Sun, 9 Aug 2026 13:15:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1786281320; bh=GaC5ILihit460FZxqqZmeMPb77gx2K+GWLRT410+nv4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=GcIXoyPpYACOoXPXTmVO8AjW4kZ9Tx1khHigfSWz9aGhg45hz3wmTHdkcr/Ni7r6W arwA0XWL2A0//RJn18w6dXRp5w5nPAPEaZG5aOHqymcCvDVGQ0F+t6cFkjSGmy+Rro Qp+zuZDHR+YgvvUb0rbp3ov7VffdJzaHNYQbL52fe3ZX8zBnjkujrDlObsGRhXnLRY sjB/2BXSpJWX+aM1qGuFH3fNw1GVRO2/2WK++jzLheeKX+acmzzC0NPZO7zX4ZF/K5 UY3DccriQ1PVu5Ksp6YHHYIEH91DJ9YoOaWuPfedk2tQH7AVIxSMBx36T4G1k3yvnV crGTh7HWz5x6w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B793C5AD68; Sun, 9 Aug 2026 13:15:20 +0000 (UTC) From: Cody Kang via B4 Relay Date: Sun, 09 Aug 2026 21:14:11 +0800 Subject: [PATCH v2 02/17] dt-bindings: phy: add SpacemiT K3 Innosilicon DP PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260809-k3-display-v2-2-327d7910bf71@gmail.com> References: <20260809-k3-display-v2-0-327d7910bf71@gmail.com> In-Reply-To: <20260809-k3-display-v2-0-327d7910bf71@gmail.com> To: David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Vinod Koul , Neil Armstrong , Haylen Chu , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yao Zi , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Guodong Xu Cc: dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org, Cody Kang X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1786281298; l=2433; i=codykang.hk@gmail.com; s=codykang; h=from:subject:message-id; bh=XomvK7OQWB2BpQ6NfJVtgaEE/SQQ/w/1buDPgY2JWZE=; b=OS0Mdz446kIKQUNz8sGws3u9JiiUbHKzMIA2ZX5KN9NECBOZFp2U87rcrgLZkoSyxKZTxfjVD I2sF9J1v23OD9WYP68abUdwsWu2fYWGq5R4NAtsNt0jx212CFwm5Kkx X-Developer-Key: i=codykang.hk@gmail.com; a=ed25519; pk=Osn6/cs9Su/mHHw4P19cmVc3v2FMQfiWahjsN0vEkuk= X-Endpoint-Received: by B4 Relay for codykang.hk@gmail.com/codykang with auth_id=895 X-Original-From: Cody Kang Reply-To: codykang.hk@gmail.com From: Cody Kang The SpacemiT K3 DisplayPort controller drives its four transmit lanes through an integrated Innosilicon DP PHY, one PHY per controller. Add a binding so the controller can reference its transmit PHY and the pixel clock the PHY's PLL sources. The PHY's registers are interleaved with its parent controller's inside one MMIO window, so it owns neither a reg nor a reset and is modelled as a child of the controller. It exposes its PLL-generated pixel clock through #clock-cells, so the APMU pixel-clock mux can select it as a parent through the clock framework. Reviewed-by: Rob Herring (Arm) Signed-off-by: Cody Kang --- v2: - add Reviewed-by: Rob Herring (Arm) --- .../bindings/phy/spacemit,k3-inno-dp-phy.yaml | 48 ++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/spacemit,k3-inno-dp-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k3-inno-dp-phy.yaml new file mode 100644 index 0000000000000..f8f1ef3729511 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/spacemit,k3-inno-dp-phy.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/spacemit,k3-inno-dp-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K3 Innosilicon DisplayPort PHY + +maintainers: + - Cody Kang + +description: + Innosilicon four-lane DisplayPort transmit PHY integrated in the SpacemiT + K3 SoC, one per DisplayPort controller. Its registers are interleaved with + the controller's own inside a single register window, so it is described as + a child of the controller and owns neither a reg nor a reset. + + The PHY provides the pixel clock its PLL generates, which the APMU + pixel-clock mux takes as one of its inputs. + +properties: + compatible: + const: spacemit,k3-inno-dp-phy + + "#phy-cells": + const: 0 + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + +required: + - compatible + - "#phy-cells" + - "#clock-cells" + +additionalProperties: false + +examples: + - | + phy { + compatible = "spacemit,k3-inno-dp-phy"; + #phy-cells = <0>; + #clock-cells = <0>; + clock-output-names = "edp0_pll_pxclk"; + }; -- 2.43.0