From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45B6832F76D for ; Mon, 10 Aug 2026 15:57:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786377428; cv=none; b=hzWzEjZahaR6Uv+UtxdiCAH/HirByika32OjIi1mrbxOofc/uDDdgLWWLJf7kQW3MDKCsH9v5UvitdJSzpjvGwlPPv+wW80EMzl7SkkQlIE8n5CPLsrKbE9Sc1WCMOMdKVu882mAW+GtcXpUUO4IsdXut1rMe0wMUksoZAg1bNk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786377428; c=relaxed/simple; bh=RgJ39QoXbfOIc7AThxoNVRBLkPgXZe+Arw6qmIws0yQ=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=f2ZiYl5NNfOXdMTlIbQGBu2pqz8XjG67E7dVVPiO3vQ+B7jmj7zqytJq4mTdIrsiXrmAArY36wBIzU+e2xYlIwpdVQQSuT2Q2DL8Rm2jgB3Bdgu5iUdlv1aACqlsE1G980Do9NSK2KECEZMlzzuYUfm9B9R0pEipAk1Iu0hR9dw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Zeg9FNUM; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Zeg9FNUM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1592E1F000E9; Mon, 10 Aug 2026 15:57:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786377426; bh=F8KMGkDAu8YfisZR65YDGzCtBVE/c5WiRa/IXVQny+k=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=Zeg9FNUMM2KrxPAAWXESkFjWTVPWBRERSBkvOYk5/S6uyldbHHk3bnMYGSeZGR+uD h9ua0GAJofD6qVA5EL9nA56XDP8Q3MY3AUZbSwgcySg3ZIdzjfmoydBrKALHRq+Hqd TUrhsbPIxhk94eGNiT2lU9UrMeSraHgvHXXNuLCBjrgiTcepzZV7+sDgc43zAqMNY4 09KmBuTKU3UiRdHQApqlvfY3VYBSzCgiw9wECgr3f6xVJN895ZQN5V9g7/iOS1rFBe +kagO+ycU3ojYnGkJAx8EewEr6/MYZzuQE0JwpAMU4fE7dQKuidPYYzFf1SQiQ6xdi DaHE0PRaYRGmQ== Date: Mon, 10 Aug 2026 16:57:00 +0100 From: Conor Dooley To: Aleksa Paunovic Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Will Deacon , Peter Zijlstra , Mark Rutland , Yury Norov , Djordje Todorovic , Rasmus Villemoes , Charlie Jenkins , Jessica Clarke , Samuel Holland , Paul Walmsley , Boqun Feng , Gary Guo , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Chao-ying Fu , Aleksandar Rikalo Subject: Re: [PATCH v4] riscv: Use Zalrsc extension to implement atomic functions Message-ID: <20260810-preoccupy-earwig-c8d98044c1da@spud> References: <20260723-p8700-zalrsc-v4-1-59c21b252e29@htecgroup.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="uy53EvrMdPjGy9dT" Content-Disposition: inline In-Reply-To: <20260723-p8700-zalrsc-v4-1-59c21b252e29@htecgroup.com> --uy53EvrMdPjGy9dT Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Jul 23, 2026 at 05:51:53PM +0200, Aleksa Paunovic wrote: > From: Chao-ying Fu >=20 > MIPS P8700 does not natively support Zaamo instructions. > They are emulated with Zalrsc extension instructions instead [1]. > Since the emulation is implemented through M-mode traps in the SBI > layer, it is best to avoid using these instructions wherever possible on > the P8700. >=20 > Implement kernel atomic operations using LR/SC sequences only. > This is achieved by using the errata mechanism, with minimal > interference on other cores. This does not seem appropriate, you don't have an actual erratum. Rather, you don't meet the minimum extension requirements that linux currently has and want to avoid emulation. >=20 > Signed-off-by: Chao-ying Fu > Signed-off-by: Aleksandar Rikalo > Co-developed-by: Aleksa Paunovic > Signed-off-by: Aleksa Paunovic >=20 > [1] https://mips.com/wp-content/uploads/2026/03/MIPS_P8700_P8700-F_Progra= mmers_Reference_Guide_Rev1.86_2-17-2026.pdf This should be a Link: tag, and be above the signoffs. >=20 > --- > The patch was tested on QEMU configured to emulate an eight-hart MIPS P87= 00 CPU. > Testing done since v3: futex kselftests and perf futex tests. These tests= caught the issues described below. > The same tests were executed on the Boston board with a single-hart P8700= core. >=20 > Since the main issue was with an incorrectly written erratum, it shouldn'= t affect Vladimir's version [1]. > However, since chips supporting only one part of the A extension are rare= , we believe it might be > better to address this using the alternative mechanism, instead of demand= ing that the wider community > relax the A extension requirement. Alternatives, sure. Relaxing the A extension requirement on the other hand basically makes no difference, if we have to insert an alternative into anything using AMO instructions, may as well do it properly and support Zal= rsc only systems rather than abuse the errata mechanisms. Any multiplatform ker= nel (so anything provided by a distro) is going to turn on any errata that are = not listed as being non-portable. The minimum requirements have been known for a long time too, since the port was merged, so I personally don't feel charitable here. Your firmware already can deal with the emulation, so I don't really see why we should be adding alternatives because people selling (or buying) IP cannot be bothered to meet the extremely basic minimum requirements of the software they want to support. >=20 > Changes in v4: > - The amo part of the ALT_TEST_AND_OP_BIT_ORD erratum erroneously hardcod= ed zero as the destination register. > This is fixed in v4. > - futex.h was missing the ANDN case. > - Link to v3: https://lore.kernel.org/r/20250901-p8700-zalrsc-v3-1-ec64fa= bbe093@htecgroup.com >=20 > Changes in v3: > - Use alternatives to replace AMO instructions with LR/SC > - Rebase on Alexandre Ghiti's "for-next" branch. > - Link to v2: https://lore.kernel.org/linux-riscv/20241225082412.36727-1-= arikalo@gmail.com/ >=20 > Links: > [1] https://lore.kernel.org/linux-riscv/20260120-lrsc-only-v2-0-a522e640d= 27d@mobileye.com/ >=20 > Signed-off-by: Aleksa Paunovic > --- > arch/riscv/Kconfig.errata | 11 ++ > arch/riscv/errata/mips/errata.c | 13 +- > arch/riscv/include/asm/atomic.h | 29 ++-- > arch/riscv/include/asm/bitops.h | 28 ++-- > arch/riscv/include/asm/cmpxchg.h | 9 +- > arch/riscv/include/asm/errata_list.h | 215 +++++++++++++++++++++= ++++++ > arch/riscv/include/asm/errata_list_vendors.h | 3 +- > arch/riscv/include/asm/futex.h | 40 ++--- > arch/riscv/kernel/entry.S | 10 +- > 9 files changed, 290 insertions(+), 68 deletions(-) >=20 > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata > index 3c945d086c7d0266b685f9506d58b0662af071c4..cd5bd5e8eb395418c3ad103db= d836c775b7fd901 100644 > --- a/arch/riscv/Kconfig.errata > +++ b/arch/riscv/Kconfig.errata > @@ -44,6 +44,17 @@ config ERRATA_MIPS_P8700_PAUSE_OPCODE > =20 > If you are not using the P8700 processor, say n. > =20 > +config ERRATA_MIPS_P8700_AMO_ZALRSC > + bool "Replace AMO instructions with LR/SC on MIPS P8700" > + depends on ERRATA_MIPS && 64BIT > + default n Why is this default n if your platform does not work without it? Cheers, Conor. --uy53EvrMdPjGy9dT Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCann0zAAKCRB4tDGHoIJi 0pV0AP9dFi5zIRbiUP/yTcCr4NiRk1C1kjFuGwY4WAU40n22tgD/bLTz/Kw7ydAO N+l2FVIBjDFpvTaqZiYaRJheaTQSAQ0= =qtR+ -----END PGP SIGNATURE----- --uy53EvrMdPjGy9dT--