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Mon, 10 Aug 2026 07:14:39 -0700 (PDT) Received: from deb05.proceq.com ([213.160.61.66]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-480021509a5sm32680580f8f.16.2026.08.10.07.14.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Aug 2026 07:14:38 -0700 (PDT) From: Mehmet Fide To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , Sasha Levin , Larisa Grigore , James Clark , Mark Brown , Vladimir Oltean , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6.12.y] spi: spi-fsl-dspi: Avoid setup_accel logic for DMA transfers Date: Mon, 10 Aug 2026 16:14:37 +0200 Message-ID: <20260810141437.2805389-1-mehmet.fide@gmail.com> X-Mailer: git-send-email 2.54.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Please consider commit cac7e5054115 ("spi: spi-fsl-dspi: Avoid setup_accel logic for DMA transfers") for 6.12.y. It is in mainline since v6.17 and applies cleanly to 6.12.y. It went in as a cleanup, so it carries neither a Fixes: tag nor a stable tag, but on vf610 the logic it removes corrupts data in DMA mode, in two ways: 1. For an odd number of bytes the accel logic packs into 16 bit frames and computes the word count as len / 2, so a 5 byte transfer puts 4 bytes in the first DMA transfer and leaves the last byte to a second one with different timing. 2. With SPI_LSB_FIRST the accel helpers byte swap through cpu_to_be16(), which combines with the hardware LSBFE bit and puts multi byte transfers on the wire in the wrong byte order. Both are visible on a Colibri VF50 (vf610, DSPI in DMA mode), and both go away with this commit, which is what we have been carrying locally against 6.12 to get correct transfers. Every stable tree older than 6.17 is affected in the same way. Thanks, Mehmet