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From: Peter Zijlstra <peterz@infradead.org>
To: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Andi Kleen <ak@linux.intel.com>,
	Eranian Stephane <eranian@google.com>,
	linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	Dapeng Mi <dapeng1.mi@intel.com>, Zide Chen <zide.chen@intel.com>,
	Falcon Thomas <thomas.falcon@intel.com>,
	Xudong Hao <xudong.hao@intel.com>
Subject: Re: [Patch v3 8/8] perf/x86/intel: Prevent drain_pebs() reentry
Date: Tue, 11 Aug 2026 10:22:56 +0200	[thread overview]
Message-ID: <20260811082256.GT48970@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <da08527f-642b-4f77-89a6-43f42e12d114@linux.intel.com>

On Tue, Aug 11, 2026 at 09:39:23AM +0800, Mi, Dapeng wrote:
> 
> On 8/10/2026 9:01 PM, Peter Zijlstra wrote:
> > On Fri, Jul 17, 2026 at 04:03:42PM +0800, Dapeng Mi wrote:
> >> The PEBS buffer is shared by all events on a CPU, so drain_pebs() must
> >> not run concurrently. If it is reentered, one instance may observe stale
> >> buffer state and potentially access out-of-bound memory.
> >>
> >> Most invocations happen in NMI context, which naturally prevents reentry.
> >> However, drain_pebs() is also reachable from process context via
> >> intel_pmu_drain_pebs_buffer().
> >>
> >> In those paths, the PMU is often already disabled, but not guaranteed.
> >> For example, __intel_pmu_pebs_disable() only disables the target counter,
> >> so other active counters can still raise a PMI and interrupt an in-flight
> >> drain_pebs().
> >>
> >> Introduce __intel_pmu_quiesce() and __intel_pmu_resume() helpers and
> >> use them in intel_pmu_drain_pebs_buffer() to disable the full PMU
> >> around the drain_pebs() call, preventing reentry.
> >>
> > It is not at all clear to me where the exact recursion happens. (The
> > word you're looking for was recursion, not concurrent).
> 
> Yes, the word "concurrently" is not accurate, reentry is the more accurate
> word.
> 
> Currently drain_pebs() would be called in two places, one is the in the PMI
> handler, like handle_pmi_common(). The other place is
> intel_pmu_drain_pebs_buffer() which is from process context.
> 
> So when intel_pmu_drain_pebs_buffer() is calling drain_pebs(), if there is
> an active PEBS event triggering PMI, it would interrupt current in-flight
> drain_pebs() and lead to drain_pebs() reentry.

What is the actual callchain here?

Because the one I'm thinking off is:

  perf_ctx_disable();
  perf_ctx_sched_task_cb()
    x86_pmu_sched_task()
      intel_pmu_sched_task()
	intel_pmu_pebs_sched_task()
	  intel_pmu_drain_pebs_buffer();
  perf_ctx_enable();

And that one has the full pmu disabled, because of context switch etc.
And then there is one in perf_read():

  pmu->read()
    intel_pmu_read_event()
      pmu_enabled = cpuc->enabled;
      cpuc->enabled = 0;
      if (pmu_enabled)
        intel_pmu_disable_all();
      intel_pmu_drain_pebs_buffer();
      cpuc->enabled = pmu_enabled;
      if (pmu_enabled)
        intel_pmu_enable_all();

So what specific callchain is going sideways?

  reply	other threads:[~2026-08-11  8:51 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-17  8:03 [Patch v3 0/8] perf/x86: Miscellaneous PMU bug fixes and optimizations Dapeng Mi
2026-07-17  8:03 ` [Patch v3 1/8] perf/x86: Unregister PMI handler on PMU init failure Dapeng Mi
2026-07-17  8:03 ` [Patch v3 2/8] perf/x86: Free hybrid state " Dapeng Mi
2026-07-17  8:03 ` [Patch v3 3/8] perf/x86: Guard intel_pmu_cpu_dead() against invalid hybrid PMU casts Dapeng Mi
2026-07-17  8:03 ` [Patch v3 4/8] perf/x86/intel: Unwind cpuc state if PEBS buffer setup fails Dapeng Mi
2026-07-17  8:03 ` [Patch v3 5/8] perf/x86: Remove stale fixed counter helper and fix hybrid PMU access Dapeng Mi
2026-07-17  8:03 ` [Patch v3 6/8] perf/x86/intel: Fix intel_cap handling on hybrid PMUs Dapeng Mi
2026-08-10 12:18   ` Peter Zijlstra
2026-08-10 12:25     ` Mi, Dapeng
2026-07-17  8:03 ` [Patch v3 7/8] perf/x86: Optimize ACR handling in match_prev_assignment() Dapeng Mi
2026-07-17  8:03 ` [Patch v3 8/8] perf/x86/intel: Prevent drain_pebs() reentry Dapeng Mi
2026-08-10 13:01   ` Peter Zijlstra
2026-08-11  1:39     ` Mi, Dapeng
2026-08-11  8:22       ` Peter Zijlstra [this message]
2026-08-11 10:00         ` Mi, Dapeng
2026-07-21 14:58 ` [Patch v3 0/8] perf/x86: Miscellaneous PMU bug fixes and optimizations Chen, Zide
2026-08-10  9:06 ` Mi, Dapeng

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