From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12BDA449EB8 for ; Tue, 11 Aug 2026 14:33:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786458820; cv=none; b=r39yIwk+D9LFW9QFG7BKsi5eOAVkBgO2g4Hpv0lk04a8C8ZVi5TYxVSAVaeZhUnHlqddGkzKm5T4VYFwlgy4+Lw8gAfJaIBKjOx8sfnKPzdPsqU4KO7/g/D0n8BhVH2dtAMIpVRTrrcMMc1eKHcREekvq4vMrCHu4OLM96WAOl4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786458820; c=relaxed/simple; bh=I3dRmbBpdwny4y/7VrHAWNz1deG+tVyE+EN7OXSUR4M=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=M73t6XUyrm06jRnJYjXxzXI7dys4pyhYCsM7fTmd30099JOcQlWHtDQ+8y2ETV23/C1Kg3vpQKo5Dz9IdWdPAYDxV2b72gKJs/vXJi3REuHhh6jRhrEiskq1cphO1ayE7SOKe3H7RRbvVKhg9sSi89Dz3cPi550PRyY6zrq6ZIo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=MF84XBJt; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="MF84XBJt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1786458816; bh=I3dRmbBpdwny4y/7VrHAWNz1deG+tVyE+EN7OXSUR4M=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=MF84XBJtAwfyV0rHzkGfhyaKFX7bViz0e8PRCWlDM6QHI9852mB8cbevnBEK/7ErY 5uTudJwqEQxZDqZMS2hePSNHWI5aCpqkTHzfMFdOu09Ug6O8haih6u2Dkt2h4wO8+i ZNaMnGhaL7CS/QPIoVQqgWVNkEbjpUH1jUNuWN0DwjNoxoCf0TR6fpOr7lghXwbprW Std8Wxz79R1W0/ZYfyKX3DPaeUa601f4OwyfwFjJQ1w7w18Hg2wtr0oh3lbKd6Lu/8 g4alnQqG1MkRzPWmt61LgzPiqb/KwNY6tvROSlge+yQ1ROD5PVa7Mkj4y0vgj0Toph zVbxzKPlUDyUA== Received: from fedora-21.home (unknown [100.64.0.11]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange secp256r1 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbrezillon) by bali.collaboradmins.com (Postfix) with ESMTPSA id 8FB8A17E0048; Tue, 11 Aug 2026 16:33:35 +0200 (CEST) Date: Tue, 11 Aug 2026 16:33:30 +0200 From: Boris Brezillon To: Nicolas Frattaroli Cc: Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Grant Likely , Heiko Stuebner , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, kernel@collabora.com Subject: Re: [PATCH v3 2/3] drm/panthor: Revisit reqs_lock handling in flush/reset paths Message-ID: <20260811163330.6b0d302a@fedora-21.home> In-Reply-To: <20260811-panthor-cache-flush-fix-v3-2-47d2c1bb1dab@collabora.com> References: <20260811-panthor-cache-flush-fix-v3-0-47d2c1bb1dab@collabora.com> <20260811-panthor-cache-flush-fix-v3-2-47d2c1bb1dab@collabora.com> Organization: Collabora X-Mailer: Claws Mail 4.4.0 (GTK 3.24.52; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Tue, 11 Aug 2026 16:08:32 +0200 Nicolas Frattaroli wrote: > panthor_gpu_flush_caches() and panthor_gpu_soft_reset() acquire their > reqs_lock spinlock with the IRQ-disabling variants of the spinlocking > functions. This isn't necessary, as the lock is never taken from an > atomic context, as Panthor uses threaded interrupt handlers. The result > of this overly strict locking is that IRQs may be disabled more > frequently and for longer than they should be, resulting in increased > system latency. > > Switch the locking to use non-IRQ-disabling scoped_guard statements for > locking. The wait_event_timeout read of pending_reqs outside of the > spinlock is fine as wait_event_timeout is a memory barrier according to > the Linux Memory Model. > > Fixes: 5cd894e258c4 ("drm/panthor: Add the GPU logical block") > Signed-off-by: Nicolas Frattaroli Reviewed-by: Boris Brezillon > --- > drivers/gpu/drm/panthor/panthor_gpu.c | 66 ++++++++++++++++------------------- > 1 file changed, 30 insertions(+), 36 deletions(-) > > diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c > index 68e2dd2527df..cb5319d1c5de 100644 > --- a/drivers/gpu/drm/panthor/panthor_gpu.c > +++ b/drivers/gpu/drm/panthor/panthor_gpu.c > @@ -330,37 +330,32 @@ int panthor_gpu_flush_caches(struct panthor_device *ptdev, > u32 l2, u32 lsc, u32 other) > { > struct panthor_gpu *gpu = ptdev->gpu; > - unsigned long flags; > int ret = 0; > > /* Serialize cache flush operations. */ > guard(mutex)(&ptdev->gpu->cache_flush_lock); > > - spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags); > - trace_gpu_cache_flush_start(ptdev->base.dev, l2, lsc, other); > - if (!(ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED)) { > - ptdev->gpu->pending_reqs |= GPU_IRQ_CLEAN_CACHES_COMPLETED; > - gpu_write(gpu->iomem, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other)); > - } else { > - ret = -EIO; > - } > - spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags); > - > - if (ret) { > - trace_gpu_cache_flush_end(ptdev->base.dev, l2, lsc, other); > - return ret; > + scoped_guard(spinlock, &ptdev->gpu->reqs_lock) { > + trace_gpu_cache_flush_start(ptdev->base.dev, l2, lsc, other); > + if (!(ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED)) { > + ptdev->gpu->pending_reqs |= GPU_IRQ_CLEAN_CACHES_COMPLETED; > + gpu_write(gpu->iomem, GPU_CMD, GPU_FLUSH_CACHES(l2, lsc, other)); > + } else { > + trace_gpu_cache_flush_end(ptdev->base.dev, l2, lsc, other); > + return -EIO; > + } > } > > if (!wait_event_timeout(ptdev->gpu->reqs_acked, > !(ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED), > msecs_to_jiffies(100))) { > - spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags); > - if ((ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED) != 0 && > - !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED)) > - ret = -ETIMEDOUT; > - else > - ptdev->gpu->pending_reqs &= ~GPU_IRQ_CLEAN_CACHES_COMPLETED; > - spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags); > + scoped_guard(spinlock, &ptdev->gpu->reqs_lock) { > + if ((ptdev->gpu->pending_reqs & GPU_IRQ_CLEAN_CACHES_COMPLETED) != 0 && > + !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_CLEAN_CACHES_COMPLETED)) > + ret = -ETIMEDOUT; > + else > + ptdev->gpu->pending_reqs &= ~GPU_IRQ_CLEAN_CACHES_COMPLETED; > + } > } > > trace_gpu_cache_flush_end(ptdev->base.dev, l2, lsc, other); > @@ -383,27 +378,26 @@ int panthor_gpu_soft_reset(struct panthor_device *ptdev) > { > struct panthor_gpu *gpu = ptdev->gpu; > bool timedout = false; > - unsigned long flags; > > - spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags); > - if (!drm_WARN_ON(&ptdev->base, > - ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED)) { > - ptdev->gpu->pending_reqs |= GPU_IRQ_RESET_COMPLETED; > - gpu_write(gpu->irq.iomem, INT_CLEAR, GPU_IRQ_RESET_COMPLETED); > - gpu_write(gpu->iomem, GPU_CMD, GPU_SOFT_RESET); > + scoped_guard(spinlock, &ptdev->gpu->reqs_lock) { > + if (!drm_WARN_ON(&ptdev->base, > + ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED)) { > + ptdev->gpu->pending_reqs |= GPU_IRQ_RESET_COMPLETED; > + gpu_write(gpu->irq.iomem, INT_CLEAR, GPU_IRQ_RESET_COMPLETED); > + gpu_write(gpu->iomem, GPU_CMD, GPU_SOFT_RESET); > + } > } > - spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags); > > if (!wait_event_timeout(ptdev->gpu->reqs_acked, > !(ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED), > msecs_to_jiffies(100))) { > - spin_lock_irqsave(&ptdev->gpu->reqs_lock, flags); > - if ((ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED) != 0 && > - !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_RESET_COMPLETED)) > - timedout = true; > - else > - ptdev->gpu->pending_reqs &= ~GPU_IRQ_RESET_COMPLETED; > - spin_unlock_irqrestore(&ptdev->gpu->reqs_lock, flags); > + scoped_guard(spinlock, &ptdev->gpu->reqs_lock) { > + if ((ptdev->gpu->pending_reqs & GPU_IRQ_RESET_COMPLETED) != 0 && > + !(gpu_read(gpu->irq.iomem, INT_RAWSTAT) & GPU_IRQ_RESET_COMPLETED)) > + timedout = true; > + else > + ptdev->gpu->pending_reqs &= ~GPU_IRQ_RESET_COMPLETED; > + } > } > > if (timedout) { >