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Sat, 15 Aug 2026 23:24:00 -0700 (PDT) From: =?UTF-8?q?Chang=20Jiong=28=E5=B8=B8=E7=82=AF=29?= To: intel-gfx@lists.freedesktop.org Cc: =?UTF-8?q?Chang=20Jiong=28=E5=B8=B8=E7=82=AF=29?= , stable@vger.kernel.org, Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , David Airlie , Simona Vetter , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , =?UTF-8?q?Micha=C5=82=20Grzelak?= , intel-xe@lists.freedesktop.org (open list:INTEL DRM DISPLAY FOR XE AND I915 DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2] drm/i915/cdclk: Don't force cd2x pipe select on Xe3 in bxt_sanitize_cdclk() Date: Sun, 16 Aug 2026 14:23:44 +0800 Message-ID: <20260816062344.796615-1-xspeed1989@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since commit 2ee8dbd880b1 ("drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL without a full PLL re-enable") bxt_sanitize_cdclk() normalizes the CD2X pipe select field of the CDCLK_CTL readback to PIPE_NONE before comparing against the expected value. However bxt_cdclk_ctl() does not include the CD2X pipe select field at all on DISPLAY_VER() >= 30, so on Xe3 (PTL) the normalized readback (pipe field forced to the PIPE_NONE encoding, 0b111) can never match the expected value (pipe field 0). The comparison now fails on every boot and we always take the full CDCLK PLL disable+re-enable path with the BIOS framebuffer actively scanning out - exactly what this code was trying to avoid. On a Panther Lake laptop (Arc B390, 8086:b080, eDP 3120x2080@120) this causes "CPU pipe A FIFO underrun" during probe and persistent full-screen scanout corruption for the first KMS client (the SDDM greeter); the corruption lasts until the next full modeset. Only normalize the CD2X pipe select field on platforms where bxt_cdclk_ctl() actually programs it, mirroring its DISPLAY_VER() check. Fixes: 2ee8dbd880b1 ("drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL without a full PLL re-enable") Cc: stable@vger.kernel.org Signed-off-by: Chang Jiong(常炯) --- v2: No code changes. Resent with From matching Signed-off-by (v1 was sent from 304750714@qq.com, which is not on the Intel CI allowlist). drivers/gpu/drm/i915/display/intel_cdclk.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 7bc9b956554b..0438f5ac78c0 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2366,8 +2366,10 @@ static void bxt_sanitize_cdclk(struct intel_display *display) * dividers both syncing to an active pipe, or asynchronously * (PIPE_NONE). */ - cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); - cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); + if (DISPLAY_VER(display) < 30) { + cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); + cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); + } if (cdctl != expected) { if (DISPLAY_VER(display) < 20) { -- 2.55.0