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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?j5fuKq5IzcyDSqgPMwJBMjjgeecpHvPqaldEKF42czzp2BqluCSntZi/TbBg?= =?us-ascii?Q?p74LGxR9IGyGdb7ZXcN+r3vhZC4D6ero6YsToxFRh0kagkdLyKSsahjL0bEl?= =?us-ascii?Q?IidMYlu9x8/RoKwgBrAQApe9RagIU1HUtcTykC8IvQSiq9ku/DSZsNIUOMay?= =?us-ascii?Q?DcxIkFk0p72048r/poYbcb83Mv91Noehi8gFfERgby64f2VWiggKyM3DD3ln?= =?us-ascii?Q?IfWo+NMuHzdPKZVubqurcfhi7HoasoNZrJTnmoltrqy5fL5W47BM09z5aQSQ?= =?us-ascii?Q?kstZgiNRNObR8Kjf+JISK008RRbIJ/7ARLbAjnNOrQ6XHLLVCjm6NjoXDspt?= =?us-ascii?Q?wp8pMKZFt7kf1bFLF1tsI3Xf3XK+ky1Lcz589ihKXM9TPC8p+qRsdyUZXW4I?= =?us-ascii?Q?l8S11N63LtWF8GPLVctPOWpI9Kk9bXROd5w92eF3O9yUKzxZIg/C1xtVyQXs?= =?us-ascii?Q?gCOF1TLskVyU2vguM7plI32Kq//gy08+mopWSvRQxALxFxY64eYKN5f3HxSB?= =?us-ascii?Q?N90sirjCB+rVF+evL38gOb6O14BIUo0/PTOWX8J0nxXiaAUeX3lWwDse3hzb?= =?us-ascii?Q?BJJpU1tvddF8IEB29fYoZ+1kNQABx2jNK13/asFB0Td3jytbZpESWUeDipaD?= =?us-ascii?Q?Ju68Nxy+/hgqoB+cgaE5hNTyMbkPH+Buc+0ctG5yGosPmbkeRi6TatKu/ciP?= =?us-ascii?Q?tMCp64lJMBhxOUVAVU7e8aI4HHAQFOSU80vTBjvaSf9GA9jmJ/vQuqukuDoT?= =?us-ascii?Q?KciC33rsUSVO54a6zYbsoFf+vWoazpBEd1WQuwzE2BcbQ+8oeZwThFd67HxQ?= =?us-ascii?Q?q5icvi7vN0IMSLWxNkf9sn45zxS0nsd9rvLA4Bp5t017cgf8bE3b0DAbHK24?= =?us-ascii?Q?uTCNHZRN99aoGqRn11cxgtHlcBLzr0Ya3VP+bLoz6jugIpfbIxZJbtUpGM7T?= =?us-ascii?Q?872chVQRQvHoKb7RcF0ZC/P8/99BI/Vy/Hfs2+RRHFd3rSLyvHPWjhZzX0i4?= =?us-ascii?Q?PsmhD7FVVywqxRIkx4yT5ODRySL23ZQ1n2AQHzMktEGj+IgPuFKjA40l6t+q?= =?us-ascii?Q?EQHi06AnftL9yhja2q93rJFdysutCwlaGWpN5uo8/2MogUJWTnXqG5cZluZT?= =?us-ascii?Q?xSFk/gA8D/pHK6vz9e8KltiuDBFehp/jMzeYzHqLvwjfgmz5eQCWOrP/2LWp?= =?us-ascii?Q?sCboyT0wIRGLbX5HL10IgXblUL8l7+CNdXhsgp17IeggaQzizmfz6Q4CeELW?= =?us-ascii?Q?JoKtza4cqfGfTgID+gXMeIHKW/URBgfosS2HkDs45/GV9ek4JB5veIWkg5Mc?= =?us-ascii?Q?F9Oe8DsJHjCwA6yJbezMbGryzz8p38waTlbFTizdEywtwxgc0qsY7LOuxyMs?= =?us-ascii?Q?jPuGkQBlv4fchoOVrG9gngDqeAcYB+ne34U6j/7Dk5kgt+msv+BZ3g/3nm8D?= =?us-ascii?Q?2+bEpg6SbQ4AFzK/szPd5/TrH3ati1kJEKm/Wm9/UFb+LtaVW4f2DVW/A0PT?= =?us-ascii?Q?n6AVsC1p+7o0BXhK3xSpcknmujmp2pJT4+sIb3NFtuhSnAT/Q2aOtUkh1p2B?= =?us-ascii?Q?+owZODtXphhXawcSeTlMu6C9aSgjBr9NA1cDdM+dPfEk2G9aw79XhjFxbckF?= =?us-ascii?Q?xtTnNpvFWz1xcLqcxUzwrM7xLzjU3zKxdB9kNEy1PhOnN1L54tbY9yykdgvX?= =?us-ascii?Q?O0KJ+BTB+y/lUx7K9klV50mH8tk6DoBmVSH5EOWTaN9thz9o?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 65dd64c9-d40d-4120-bb74-08deff9f1044 X-MS-Exchange-CrossTenant-AuthSource: LV8PR12MB9620.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Aug 2026 16:12:57.2216 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: u144w3WIN1inFQ+qc1ZN4RlmJ0S1KMklQS+F8TljPRXtXpyw0hfti76K2uhiWamv X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH8PR12MB9789 On Fri, Aug 21, 2026 at 05:18:49PM +0200, Andrew Jones wrote: > On Fri, Aug 21, 2026 at 11:31:55AM -0300, Jason Gunthorpe wrote: > > On Fri, Aug 21, 2026 at 04:23:22PM +0200, Andrew Jones wrote: > > > > But RISC-V IOMMU is also not involved in interrupt translation. Beyond > > > > it could remap the PAs which represent the CPUs, but you are not using > > > > it that way since it is statically setup. > > > > > > > > So I'm not sure why the iommu gets an IR? Isn't it the same as ARM > > > > where the IMSIC itself just has a wack of PAs it needs to access so it > > > > calls iommu_dma_prepare_msi() to do it? > > > > > > Right, this series is only remapping IMSIC PAs, not using the IOMMU MSI > > > table. The MSI table must be disabled when second-stage translation is > > > Bare, so it cannot be used for the host mappings here. It will be needed > > > for guest interrupt files (the irqbypass series I'm also working on), > > > where this IR irqdomain can then intercept irq_set_vcpu_affinity(). > > > Also, keeping the MSI setup in this IR irqdomain avoids putting IOMMU > > > mapping knowledge in the IMSIC driver. > > > > It's ok for the IMSIC driver to call iommu_dma_prepare_msi(), that's > > the architecutre of this at least. > > > > Until you get to adding something more complicated, eg irqbypass, I'd > > suggest keeping this series simple. > > > > I guess I would wonder why the IOMMU needs to be involved in changing > > the mapping down the road, why not just reprogram the MSI-X address? > > > > For guest interrupts the MSI-X address is a guest IMSIC address. > Reprogramming it handles a guest reroute, but not vcpu migration (the > guest address stays the same while its host backing moves between > guest interrupt files and MRIFs). Linux isn't prepared to have a guest controlled MSI-X addr, AFAIK. I've wanted this for a long time but we are not there.. Does riscv absolutely require this? I suppose you have a new problem where you don't know what affinity the guest is selecting when it provides a MSI-X addr as you don't know what physical IMSIC page is under its S1 IOVA? > The IOMMU driver updates that mapping through "the hypervisor to > IOMMU driver interface", a.k.a. the IRQ domain's > irq_set_vcpu_affinity() callback. That mapping cannot be prepared > ahead of time because only the hypervisor knows the target, and it > may change later. Nicolin has a series that worked toward making ARM work properly, it is not at all like this and it isn't done with remapping domains. You want to preserve the guests physical MSI-X info directly and plub through the proper mapping so that the S1 -> S2 translation setup by the guest actually works right. If you don't do that then you can just have Linux adjust the MSI-X addr like intel does and use the RMR trick from ARM to get the IMSIC pages into the S1 IOVA. Still no need for a remapping domain. It's so complex, so I think you will have an easier time doing tiny small steps at a time.. Jason