Re: [PATCH v4 02/21] iommufd: Add iommufd_sw_map_msi()

[Jason Gunthorpe <jgg@nvidia.com>]

On Fri, Aug 21, 2026 at 07:12:15PM +0200, Andrew Jones wrote:
> > Does riscv absolutely require this? I suppose you have a new problem
> > where you don't know what affinity the guest is selecting when it
> > provides a MSI-X addr as you don't know what physical IMSIC page is
> > under its S1 IOVA?
> 
> The IOMMU MSI table operates after S1, so it matches the resulting IMSIC
> GPA. With a vIOMMU, the guest may use any MSI IOVA that its S1 maps to
> that GPA. With S1 Bare, the device uses the GPA directly. In either case
> the hypervisor provides the guest IMSIC topology and the guest interrupt
> file or MRIF target needed to program the MSI table (through the IRQ
> domain).

I suspect you should have an IRQ domain for the msiptp functionality,
but IDK what it should do... Is this basically to remap vCPUs to
pCPUs?

The viommu can set the msi_addr_pattern

The existing msi stuff can place the physical ICMC at the right spot
in the S1 to give to the viommu (Nicolin's series may be needed for
this too, I forget)

Not sure how you provide the guest MSI descriptor and have the irq
layer program it directly..

It is unfortunate you can't learn the vCPU the MSI is targetting from
the MSI descriptor, in terms of linux that's a pretty difficult choice
to implement.

Jason