From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D7FA36728D for ; Fri, 21 Aug 2026 22:16:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.199 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787350593; cv=none; b=QBKD0ajwcD3uky9mn0tPnZTXZ89ggGinhQ8cA7+Zme3zRm12/MPGpdCii5zabKksdm/3F7FabUiInL891OP11bol3H06YGBqaohHkL06JTT0GzUkeffMRVVLczdd+m+txFAGTKDH74ku2ei/OzlWBz5Rq/iAy+FPbQCA3d2kNhY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787350593; c=relaxed/simple; bh=9cK+9qTql37QYIz37WDsRcw/7LQHtdTltaYK46f9BPY=; h=Date:Mime-Version:Message-ID:Subject:From:To:Cc:Content-Type; b=h9YAbNo0AdT53xUoVgJiFoiXoHfaPpLemCGRCviAAuyNPipxNEckIFwKT6KNieTHUeMZqtyCni9EESFbLnZ45brR+/cp2EanP5HT1Pxqmk8PpWnQy67THhKXiuKhdYjN/rZN8rkFvHia5H0wv2fO9HPiRBLzwuJxGTANw4YPzz0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--dmatlack.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=W7OBsQNU; arc=none smtp.client-ip=209.85.214.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--dmatlack.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="W7OBsQNU" Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-2cccfa32670so23745465ad.2 for ; Fri, 21 Aug 2026 15:16:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1787350591; x=1787955391; darn=vger.kernel.org; h=content-transfer-encoding:content-type:cc:to:from:subject :message-id:mime-version:date:from:to:cc:subject:date:message-id :reply-to:content-type; bh=nGzjUGYctwJSzkPPOCCVrXKRANqiQHkPBAJGCUzWsl0=; b=W7OBsQNUbxIvV78WgdGbo+iV3yFsojiG1m9gx5+fWwXkSWSozCA1LGP+WNHoDxmX3g wniytQEciIoYL6/BUc3mumDVXe41wI4n9yVI8qwJedXFxxvmdped9gq9ab1ViDr0NeOC xVEVoLfLVVeHy5y+WxyJ8drhVzzQQqXOZGi47/CxwOadwrri9aXTOTShn1lwEexdz9mx J1cTrzqpFvCv+ZCd3MVvLb3iDx95JoJhtycMHM9fKDSmg0TkPJcBQSPfJOvdKMn2v9wd jhnGOIOPlAk+fKS/N4rOoLVpn08awV4IyZvDHm+Q+wRUgUbZl/yrSMdc155D0Q6aMUex +4Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1787350591; x=1787955391; h=content-transfer-encoding:content-type:cc:to:from:subject :message-id:mime-version:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to:content-type; bh=nGzjUGYctwJSzkPPOCCVrXKRANqiQHkPBAJGCUzWsl0=; b=fIUCagG8uXXBoF71oCQqQ/iWJNdiBszynmJlV2u/4ynwwwyzp+S1D0V1YklOoiVaYo nmRpMPuUgQAHtA61GVSuf4Iz/q4vVmdwsGmG+YQRifZkjYAUfDivsaWtC8x1GnHovKJ/ 7Gv6YBFvKa2xL27TtmJnJ71OfXhbi+x/H+/0BG1Kx+nlZ+Ll1gsk5IbfLW/Z9fbt7WJa Ltsi7XA37l/X1Ao7X0Ca7rOpKy6NgRURPqnDTLmToPmBsnvOX7s6rMVTKByDruQ1UmkQ 6kBkOCuVr0fyXAak+1QW8z5bjGuHd/7jSSMyP/1yx5uBapNbIQFd7t2OzcQzsDKdcMcx U/fQ== X-Forwarded-Encrypted: i=1; AHgh+Rppn0piI81LKd3+elbA1X/qlOxjXDWIs8mwA79KavjwN7uLSnQd4BIahjYOIXQEjKt5eQR+N5wKKvyj3M8=@vger.kernel.org X-Gm-Message-State: AFuF++kZIiQ3AIOEt4w7c+aOoGMf6Bk25UpMXEokgyfOp1kiY+sMNSLU WoCfLjP8NY/yx8HhqD446NEjlZMa+ZtVL8Z9Q2PQMQuXBy7cHTGlv89cedZ3Lg0NZdUAmN1Ow9L lFL9h1wthN72l6g== X-Received: from plbms11.prod.google.com ([2002:a17:903:acb:b0:2cc:e88e:423c]) (user=dmatlack job=prod-delivery.src-stubby-dispatcher) by 2002:a17:902:ef47:b0:2d6:7409:7145 with SMTP id d9443c01a7336-2d674097a77mr9729445ad.1.1787350591303; Fri, 21 Aug 2026 15:16:31 -0700 (PDT) Date: Fri, 21 Aug 2026 22:15:59 +0000 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 X-Mailer: git-send-email 2.55.0.766.g2966f0265a-goog Message-ID: <20260821221610.3570722-1-dmatlack@google.com> Subject: [pciutils PATCH v2] lspci: Determine bridge window address size from bridge_flags From: David Matlack To: Martin Mares Cc: "=?UTF-8?q?Pali=20Roh=C3=A1r?=" , David Matlack , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Helgaas Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Use bridge_flags to determine address size bits (16- vs 32-bit for I/O, 32- vs 64-bit for prefetchable memory) when displaying bridge ranges populated via PCI_FILL_BRIDGE_BASES. Commit ccf68033a452 ("lspci: Use PCI_FILL_BRIDGE_BASES to detect if range behind bridge is disabled or unsupported") introduced code in show_htype1() that reads PCI_IO_RANGE_TYPE_MASK and PCI_MEMORY_RANGE_TYPE_MASK from bridge_base_addr[]. However, bridge_base_addr[] holds base addresses without flags, as documented in lib/pci.h and implemented across backends like sysfs.c and win32-cfgmgr32.c. Because bridge_base_addr[] does not contain configuration register flag bits, masking the lower bits evaluates to zero. As a result, 32-bit I/O windows are mislabeled as "[16-bit]" and 64-bit prefetchable memory windows are mislabeled as "[32-bit]" when using PCI_FILL_BRIDGE_BASES. Fixes: ccf68033a452 ("lspci: Use PCI_FILL_BRIDGE_BASES to detect if range b= ehind bridge is disabled or unsupported") Signed-off-by: David Matlack --- v2: - Fix lspci.c to use bridge_flags[], per lib/pci.h, rather than changing the behavior of just the sysfs backend (Pali Roh=C3=A1r) v1: https://lore.kernel.org/linux-pci/20260626213047.189951-1-bhelgaas@goog= le.com/ lspci.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/lspci.c b/lspci.c index 2a14303e74f6..52fd9247aefb 100644 --- a/lspci.c +++ b/lspci.c @@ -571,10 +571,9 @@ show_htype1(struct device *d) =20 if ((p->known_fields & PCI_FILL_BRIDGE_BASES) && !io_disabled) { - io_base =3D p->bridge_base_addr[0] & PCI_IO_RANGE_MASK; + io_base =3D p->bridge_base_addr[0]; io_limit =3D io_base + p->bridge_size[0] - 1; - io_type =3D p->bridge_base_addr[0] & PCI_IO_RANGE_TYPE_MASK; - io_bits =3D (io_type =3D=3D PCI_IO_RANGE_TYPE_32) ? 32 : 16; + io_bits =3D (p->bridge_flags[0] & PCI_IORESOURCE_IO_16BIT_ADDR) ? 16= : 32; show_range("\tI/O behind bridge", io_base, io_limit, io_bits, io_dis= abled); } else if (io_type !=3D (io_limit & PCI_IO_RANGE_TYPE_MASK) || @@ -600,7 +599,7 @@ show_htype1(struct device *d) =20 if ((p->known_fields & PCI_FILL_BRIDGE_BASES) && !mem_disabled) { - mem_base =3D p->bridge_base_addr[1] & PCI_MEMORY_RANGE_MASK; + mem_base =3D p->bridge_base_addr[1]; mem_limit =3D mem_base + p->bridge_size[1] - 1; show_range("\tMemory behind bridge", mem_base, mem_limit, 32, mem_di= sabled); } @@ -616,10 +615,9 @@ show_htype1(struct device *d) =20 if ((p->known_fields & PCI_FILL_BRIDGE_BASES) && !pref_disabled) { - u64 pref_base_64 =3D p->bridge_base_addr[2] & PCI_MEMORY_RANGE_MASK; + u64 pref_base_64 =3D p->bridge_base_addr[2]; u64 pref_limit_64 =3D pref_base_64 + p->bridge_size[2] - 1; - pref_type =3D p->bridge_base_addr[2] & PCI_MEMORY_RANGE_TYPE_MASK; - pref_bits =3D (pref_type =3D=3D PCI_PREF_RANGE_TYPE_64) ? 64 : 32; + pref_bits =3D (p->bridge_flags[2] & PCI_IORESOURCE_MEM_64) ? 64 : 32= ; show_range("\tPrefetchable memory behind bridge", pref_base_64, pref= _limit_64, pref_bits, pref_disabled); } else if (pref_type !=3D (pref_limit & PCI_PREF_RANGE_TYPE_MASK) || base-commit: b41ce14da749fb44ca7940ba9797027bfa62c23e --=20 2.55.0.766.g2966f0265a-goog