The Linux Kernel Mailing List
 help / color / mirror / Atom feed
From: "Rafael J. Wysocki" <rjw@rjwysocki.net>
To: Linux PM <linux-pm@vger.kernel.org>
Cc: LKML <linux-kernel@vger.kernel.org>,
	Lukasz Luba <lukasz.luba@arm.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>,
	Dietmar Eggemann <dietmar.eggemann@arm.com>,
	Morten Rasmussen <morten.rasmussen@arm.com>,
	Vincent Guittot <vincent.guittot@linaro.org>,
	Ricardo Neri <ricardo.neri-calderon@linux.intel.com>,
	Pierre Gondois <pierre.gondois@arm.com>,
	Christian Loehle <christian.loehle@arm.com>
Subject: [PATCH v2 6/7] cpufreq: intel_pstate: EAS: Increase cost for CPUs using L3 cache
Date: Tue, 06 May 2025 22:47:53 +0200	[thread overview]
Message-ID: <2032776.usQuhbGJ8B@rjwysocki.net> (raw)
In-Reply-To: <2999205.e9J7NaK4W3@rjwysocki.net>

From: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

On some hybrid platforms some efficient CPUs (E-cores) are not connected
to the L3 cache, but there are no other differences between them and the
other E-cores that use L3.  In that case, it is generally more efficient
to run "light" workloads on the E-cores that do not use L3 and allow all
of the cores using L3, including P-cores, to go into idle states.

For this reason, slightly increase the cost for all CPUs sharing the L3
cache to make EAS prefer CPUs that do not use it to the other CPUs of
the same type (if any).

Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---

v1 -> v2:
   * Change L3 cache lookup method (the previous one doesn't always work).
   * Adjust the new comment.
   * Increase the cost for CPUs using L3 by 2 (instead of increasing it by 1)
     to make the scheduler select the CPUs without L3 more often.
   * Adjust the changelog.

---
 drivers/cpufreq/intel_pstate.c |   17 +++++++++++++++++
 1 file changed, 17 insertions(+)

--- a/drivers/cpufreq/intel_pstate.c
+++ b/drivers/cpufreq/intel_pstate.c
@@ -982,6 +982,7 @@
 			   unsigned long *cost)
 {
 	struct pstate_data *pstate = &all_cpu_data[dev->id]->pstate;
+	struct cpu_cacheinfo *cacheinfo = get_cpu_cacheinfo(dev->id);
 
 	/*
 	 * The smaller the perf-to-frequency scaling factor, the larger the IPC
@@ -994,6 +995,22 @@
 	 * of the same type in different "utilization bins" is different.
 	 */
 	*cost = div_u64(100ULL * INTEL_PSTATE_CORE_SCALING, pstate->scaling) + freq;
+	/*
+	 * Increase the cost slightly for CPUs able to access L3 to avoid
+	 * touching it in case some other CPUs of the same type can do the work
+	 * without it.
+	 */
+	if (cacheinfo) {
+		unsigned int i;
+
+		/* Check if L3 cache is there. */
+		for (i = 0; i < cacheinfo->num_leaves; i++) {
+			if (cacheinfo->info_list[i].level == 3) {
+				*cost += 2;
+				break;
+			}
+		}
+	}
 
 	return 0;
 }




  parent reply	other threads:[~2025-05-06 20:49 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-06 20:32 [PATCH v2 0/7] cpufreq: intel_pstate: Enable EAS on hybrid platforms without SMT Rafael J. Wysocki
2025-05-06 20:34 ` [PATCH v2 1/7] cpufreq/sched: schedutil: Add helper for governor checks Rafael J. Wysocki
2025-05-06 20:37 ` [PATCH v2 2/7] cpufreq/sched: Move cpufreq-specific EAS checks to cpufreq Rafael J. Wysocki
2025-05-09 23:49   ` Marek Szyprowski
2025-05-10 11:31     ` Rafael J. Wysocki
2025-05-12  6:48       ` Marek Szyprowski
2025-05-12 12:53         ` Rafael J. Wysocki
2025-05-12 17:24           ` Dietmar Eggemann
2025-05-12 17:47             ` Rafael J. Wysocki
2025-05-06 20:39 ` [PATCH v2 3/7] PM: EM: Move CPU capacity check to em_adjust_new_capacity() Rafael J. Wysocki
2025-05-06 20:41 ` [PATCH v2 4/7] PM: EM: Introduce em_adjust_cpu_capacity() Rafael J. Wysocki
2025-05-06 20:44 ` [PATCH v2 5/7] cpufreq: intel_pstate: EAS support for hybrid platforms Rafael J. Wysocki
2025-05-06 20:47 ` Rafael J. Wysocki [this message]
2025-05-06 20:48 ` [PATCH v2 7/7] cpufreq: intel_pstate: Document hybrid processor support Rafael J. Wysocki
2025-05-13 12:51 ` [PATCH v2 0/7] cpufreq: intel_pstate: Enable EAS on hybrid platforms without SMT Rafael J. Wysocki
2025-05-13 14:01   ` Rafael J. Wysocki
2025-06-29 12:28     ` Ibrahim Ansari
2025-06-30 18:51       ` Rafael J. Wysocki

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=2032776.usQuhbGJ8B@rjwysocki.net \
    --to=rjw@rjwysocki.net \
    --cc=christian.loehle@arm.com \
    --cc=dietmar.eggemann@arm.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pm@vger.kernel.org \
    --cc=lukasz.luba@arm.com \
    --cc=morten.rasmussen@arm.com \
    --cc=peterz@infradead.org \
    --cc=pierre.gondois@arm.com \
    --cc=ricardo.neri-calderon@linux.intel.com \
    --cc=srinivas.pandruvada@linux.intel.com \
    --cc=vincent.guittot@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox