From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964973AbcAZJwc (ORCPT ); Tue, 26 Jan 2016 04:52:32 -0500 Received: from gloria.sntech.de ([95.129.55.99]:52631 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964828AbcAZJw3 convert rfc822-to-8bit (ORCPT ); Tue, 26 Jan 2016 04:52:29 -0500 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Jianqun Xu Cc: Mark Brown , Sonny Rao , Caesar Wang , "open list:ARM/Rockchip SoC..." , leozwang@google.com, "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Kees Cook Subject: Re: [PATCH v3 3/9] ASoC: rockchip: i2s: add support for grabbing output clock to codec Date: Tue, 26 Jan 2016 10:52:25 +0100 Message-ID: <2073307.S3XLZp3hP0@diego> User-Agent: KMail/4.14.10 (Linux/4.2.0-1-amd64; KDE/4.14.14; x86_64; ; ) In-Reply-To: <56A57733.8020200@rock-chips.com> References: <1452865796-23527-1-git-send-email-wxt@rock-chips.com> <20160122171815.GD6588@sirena.org.uk> <56A57733.8020200@rock-chips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="utf-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jay, Am Montag, 25. Januar 2016, 09:15:31 schrieb Jianqun Xu: > 在 23/01/2016 01:18, Mark Brown 写道: > > On Fri, Jan 15, 2016 at 01:48:04PM -0800, Sonny Rao wrote: > >> On Fri, Jan 15, 2016 at 9:46 AM, Mark Brown wrote: > >>> If the I2S block is providing a clock to the CODEC then that's what the > >>> software should do so that the CODEC can gate and ungate the clock as > >>> required. This patch has the I2S block using a clock, not providing > >>> one. > >>> > >> From my read of the clock diagram for RK3288 there is a single clock > >> > >> signal (labeled "clk_i2s0") that comes out of a fractional divider, > >> and it is split such that one path gets sent to the I2S block and the > >> second path is sent to a mux after which that signal is sent to an > >> external pin that goes to the codec. > >> > >> There are separate clock gates for the two paths: one for the I2S > >> block and one after that mux before the external pin. > >> > >> I'm not sure if it's being modeled that way in the Linux code or not, > >> but at least physically I don't think this clock signal actually goes > >> through the I2S block before being sent to the codec. > > > > That's not really the issue here, the issue is that it's not the I2S > > controller that is consuming the clock so it should not be the I2S > > controller driver that ensures that the clock is enabled. The driver > > that manages the clock should be the one that uses it, like I say this > > means you should add the code to enable the clock to the CODEC driver if > > the CODEC driver needs the clock enabled. > > Agree, now we almost use the simple-card for the CODEC driver, so I > think we should enable the mclk(i2s-outclk) in the simple-card driver, > is it ? > > I found a subnode property from simple-card document: > - mclk-fs : Multiplication factor between > stream > rate and codec mclk, applied > only for > the dai-link. > But the property responsible to the factor, not care if the mclk source > clock is enabled or not. So does the simple-card driver can add support > to enable/disable mclk ? The mclk-input is part of the codec I'd think. So you'd want the clocks- property in the i2c entry describing the codec itself and implement the clk operations in the codec driver as well. See codec-drivers for da7213, da7218,max98090 and many more for reference. Heiko > >> Does that help clarify? > > > > The problem here isn't a lack of clarity in the situation.