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Shenoy" , Perry Yuan Cc: "open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)" , "open list:CPU FREQUENCY SCALING FRAMEWORK" , Mario Limonciello References: <20250206215659.3350066-1-superm1@kernel.org> <20250206215659.3350066-8-superm1@kernel.org> Content-Language: en-US From: Dhananjay Ugwekar In-Reply-To: <20250206215659.3350066-8-superm1@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-ClientProxiedBy: PN3PEPF00000184.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c04::4a) To LV8PR12MB9207.namprd12.prod.outlook.com (2603:10b6:408:187::15) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV8PR12MB9207:EE_|CY8PR12MB7291:EE_ X-MS-Office365-Filtering-Correlation-Id: 550643e2-3404-47c9-c2ef-08dd4a639842 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|1800799024; X-Microsoft-Antispam-Message-Info: =?utf-8?B?cWpjVGNtclR0c0xOZXdiZ1RRY3hJY1hHbEt5N24vZTV2dkgwd2VNcFRRQXdz?= =?utf-8?B?bEU5MHZmWU1KRlNUemhWZHlQSUdtWVBQY0l2RG5xOWhiSjg4VzZrcU42cFpB?= =?utf-8?B?TWJnaWsySTJoSXZyUGxvYVpMdGozZjRScjZYeWxmSTNMMDlQOXJLcFNISGl1?= =?utf-8?B?YnprdzFSWHJIM0hBSjVSTm1adFlrQmVHMkpvSkVXZWdjN2JkTUJKTllxSDRX?= =?utf-8?B?b2JhTG16b1hwcUdHMlJkMC9RRmI1ZUpOc0pKZ2FpcUlvRzUyT2doeUVLU2lL?= =?utf-8?B?TEVPb0c2RlAwWXVKbUZDTCtLaml2UVREbWN1djhURCtZWXZhak05dStJY05Z?= =?utf-8?B?V1hyS0x5eHN3RjVMbGlGRGFwVW83bFhxc3p5Q1oraUtPUG03VE9pTlFEbnJD?= =?utf-8?B?NHRrTkJreFhaZWFGeGI0UEh2SjhRTk5FSjNOSi81TUNxVjVuREsvR2tzVE9W?= =?utf-8?B?ME5MRUw3MllGR2hSblJYVkk4eGtveTh2N1VVZkFyRDdkVnRNTlMyWjZHRlY0?= =?utf-8?B?MXFLUGlMZkFSTk5BdHBqellaQ0JER0lUWnBoSWVramlnWkhzc3NiY1dUeDEx?= =?utf-8?B?TzFXb0huUzhuWkMxM3ZSNUJvNXd3WFhGQmpodGVkZHc3VC9HWnJZOEJkcjA4?= =?utf-8?B?WUtoY1RWN0NZSVBVRnEvNDZQNFM0RkJlVGJsRG4wL05oV3hhejlZRHovSTZr?= =?utf-8?B?NDFVeEluUWcyWFZ0RWV6TlFjMzRtYTFuSlhHOVhvTmdMd2IwMnZGejR2T2pu?= =?utf-8?B?Z1hQeWxWZ2pBeWJudm9SeXFIMFNTWklmWjV6aHBOVmt5WWVTR1E2S3BaTTdk?= =?utf-8?B?cWxZMW9MMFNnS280VGxkUGFWS2grZUJ4eWl2Wkx3T2YyS2pTRFhHTi96SThv?= =?utf-8?B?NURXQ0NoWDg0ZDZFaHZkL1hsWXl0dG9sbFgrSjR6eU9zUGYwRCtob0lyTUpE?= =?utf-8?B?bXhrZE1TM2JmMWxqQnMxemZEaG43UnU1UWpPdnQwUFE3d3lzQkNoWW10TjNw?= =?utf-8?B?OEZSclVoOHpuRDBzaTJvYS9YQUhHbWVSY1FPK2pJRm9tZm9SR1p1L3VjdzBK?= =?utf-8?B?b1JnRTNENGhLU000ZU5Ca3kxa2tnaFljTVVSUDZuaWJkcmJMbkFiZXEvVmVE?= =?utf-8?B?Z3JqMjhkWDZQTCs1c2gvTjExbDg0Z1NXcEZyN2RNRE1HdGhMck0yOVBzOWoy?= =?utf-8?B?bVVFeXRLa1owOTAyTXlSSXp2azBaVU84UWM2MHU2M3B1U0xaa2VHQ0VkM1lE?= =?utf-8?B?N0NxeHRGQi84cE1PK2NYaWRLZkVJU2V1VjFYYnQrOWQwUnJaOTlCZ1E2SGg4?= =?utf-8?B?Q0V2T015cDZXVWV5OVdYQWppbzlXRXpUazNTQm5aR2ZGU1JUakxLYjJIVUEz?= =?utf-8?B?MVdhNkFZM25kSEpQbGp6UG1Ta1RXSGJac0xZWGxCK1BndUtIS05FSXJWRys5?= =?utf-8?B?Y1E4eUJDMGxDYUFtSEtBdnZuSkJQSzg3eHhORHZPNmlpZzdRZGV0eHhrZUpP?= =?utf-8?B?UWpVbXpVUnd6ZDlXY1RDLzNLbmlvTlZZUm5qV2krMVl2dVRrRlVJaHpBa3Jj?= =?utf-8?B?R1V2SG9qK1VnUU9rUDM1alhZb0M5UmorN25IVlZUUmhNTk43T25ncDNYeVVp?= =?utf-8?B?ZXMya05kalkyaXFLcVNKRmU2ZDJhSXhCcHNQbjBTT2k4RzUyendtRUZEWHBj?= =?utf-8?B?cUd3Y3hjcFhBc3lkV3Z0dDY0ZjhBZVVBRG9nT0VvYnAvVGhvUk92WUdoTFNn?= =?utf-8?B?T2JRZCtKbWU5dUhER3lTTm5sVStyL2poQVgzaThQZUt5Tys0a1FWYndBbkFR?= =?utf-8?B?eFdDRFZ1NmZDT2Zva2Q2MWVuU29BbTcwcy85OFY3ZXdkUlJsaHJvWE8wYWFM?= =?utf-8?Q?nX2SauxjXcbiI?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV8PR12MB9207.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(376014)(366016)(1800799024);DIR:OUT;SFP:1101; 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Looks good to me, just one suggestion below, apart from that, Reviewed-by: Dhananjay Ugwekar > > Signed-off-by: Mario Limonciello > --- > arch/x86/include/asm/msr-index.h | 18 +++++++++--------- > arch/x86/kernel/acpi/cppc.c | 2 +- > drivers/cpufreq/amd-pstate-ut.c | 8 ++++---- > drivers/cpufreq/amd-pstate.c | 16 ++++++---------- > 4 files changed, 20 insertions(+), 24 deletions(-) > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index 3eadc4d5de837..f77335ebae981 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -700,15 +700,15 @@ > #define MSR_AMD_CPPC_REQ 0xc00102b3 > #define MSR_AMD_CPPC_STATUS 0xc00102b4 > > -#define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff) > -#define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff) > -#define AMD_CPPC_NOMINAL_PERF(x) (((x) >> 16) & 0xff) > -#define AMD_CPPC_HIGHEST_PERF(x) (((x) >> 24) & 0xff) > - > -#define AMD_CPPC_MAX_PERF(x) (((x) & 0xff) << 0) > -#define AMD_CPPC_MIN_PERF(x) (((x) & 0xff) << 8) > -#define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) > -#define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) > +#define AMD_CPPC_LOWEST_PERF_MASK GENMASK(7, 0) How about AMD_CPPC_"CAP"_LOWEST_PERF_MASK and > +#define AMD_CPPC_LOWNONLIN_PERF_MASK GENMASK(15, 8) > +#define AMD_CPPC_NOMINAL_PERF_MASK GENMASK(23, 16) > +#define AMD_CPPC_HIGHEST_PERF_MASK GENMASK(31, 24) > + > +#define AMD_CPPC_MAX_PERF_MASK GENMASK(7, 0) AMD_CPPC_"REQ"_MAX_PERF_MASK, just to indicate these fields belong to which register? But we can keep it as is, if you think it would be a mouthful, I'll leave it upto you. Thanks, Dhananjay > +#define AMD_CPPC_MIN_PERF_MASK GENMASK(15, 8) > +#define AMD_CPPC_DES_PERF_MASK GENMASK(23, 16) > +#define AMD_CPPC_EPP_PERF_MASK GENMASK(31, 24) > > /* AMD Performance Counter Global Status and Control MSRs */ > #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 > diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c > index d745dd586303c..d68a4cb0168fa 100644 > --- a/arch/x86/kernel/acpi/cppc.c > +++ b/arch/x86/kernel/acpi/cppc.c > @@ -149,7 +149,7 @@ int amd_get_highest_perf(unsigned int cpu, u32 *highest_perf) > if (ret) > goto out; > > - val = AMD_CPPC_HIGHEST_PERF(val); > + val = FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, val); > } else { > ret = cppc_get_highest_perf(cpu, &val); > if (ret) > diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-ut.c > index adaa62fb2b04e..2595faa492bf1 100644 > --- a/drivers/cpufreq/amd-pstate-ut.c > +++ b/drivers/cpufreq/amd-pstate-ut.c > @@ -158,10 +158,10 @@ static void amd_pstate_ut_check_perf(u32 index) > return; > } > > - highest_perf = AMD_CPPC_HIGHEST_PERF(cap1); > - nominal_perf = AMD_CPPC_NOMINAL_PERF(cap1); > - lowest_nonlinear_perf = AMD_CPPC_LOWNONLIN_PERF(cap1); > - lowest_perf = AMD_CPPC_LOWEST_PERF(cap1); > + highest_perf = FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, cap1); > + nominal_perf = FIELD_GET(AMD_CPPC_NOMINAL_PERF_MASK, cap1); > + lowest_nonlinear_perf = FIELD_GET(AMD_CPPC_LOWNONLIN_PERF_MASK, cap1); > + lowest_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1); > } > > if (highest_perf != READ_ONCE(cpudata->perf.highest_perf) && > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c > index 71636bd9884c8..cd96443fc117f 100644 > --- a/drivers/cpufreq/amd-pstate.c > +++ b/drivers/cpufreq/amd-pstate.c > @@ -89,11 +89,6 @@ static bool cppc_enabled; > static bool amd_pstate_prefcore = true; > static struct quirk_entry *quirks; > > -#define AMD_CPPC_MAX_PERF_MASK GENMASK(7, 0) > -#define AMD_CPPC_MIN_PERF_MASK GENMASK(15, 8) > -#define AMD_CPPC_DES_PERF_MASK GENMASK(23, 16) > -#define AMD_CPPC_EPP_PERF_MASK GENMASK(31, 24) > - > /* > * AMD Energy Preference Performance (EPP) > * The EPP is used in the CCLK DPM controller to drive > @@ -445,12 +440,13 @@ static int msr_init_perf(struct amd_cpudata *cpudata) > > perf.highest_perf = numerator; > perf.max_limit_perf = numerator; > - perf.min_limit_perf = AMD_CPPC_LOWEST_PERF(cap1); > - perf.nominal_perf = AMD_CPPC_NOMINAL_PERF(cap1); > - perf.lowest_nonlinear_perf = AMD_CPPC_LOWNONLIN_PERF(cap1); > - perf.lowest_perf = AMD_CPPC_LOWEST_PERF(cap1); > + perf.min_limit_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1); > + perf.nominal_perf = FIELD_GET(AMD_CPPC_NOMINAL_PERF_MASK, cap1); > + perf.lowest_nonlinear_perf = FIELD_GET(AMD_CPPC_LOWNONLIN_PERF_MASK, cap1); > + perf.lowest_perf = FIELD_GET(AMD_CPPC_LOWEST_PERF_MASK, cap1); > WRITE_ONCE(cpudata->perf, perf); > - WRITE_ONCE(cpudata->prefcore_ranking, AMD_CPPC_HIGHEST_PERF(cap1)); > + WRITE_ONCE(cpudata->prefcore_ranking, FIELD_GET(AMD_CPPC_HIGHEST_PERF_MASK, cap1)); > + > return 0; > } >