From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B52A7CE79B0 for ; Wed, 20 Sep 2023 10:45:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234063AbjITKpr (ORCPT ); Wed, 20 Sep 2023 06:45:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234444AbjITKpV (ORCPT ); Wed, 20 Sep 2023 06:45:21 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E82EA1B9; Wed, 20 Sep 2023 03:45:02 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B98951FB; Wed, 20 Sep 2023 03:45:39 -0700 (PDT) Received: from [10.163.63.253] (unknown [10.163.63.253]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 84ACA3F5A1; Wed, 20 Sep 2023 03:44:59 -0700 (PDT) Message-ID: <21bc7889-e456-e95b-7155-2563f1b6c3e4@arm.com> Date: Wed, 20 Sep 2023 16:14:56 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.0 Subject: Re: [PATCH V5 - RESEND 2/3] coresight: etm: Make cycle count threshold user configurable Content-Language: en-US To: Suzuki K Poulose , linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Will Deacon , Mike Leach , Jonathan Corbet , linux-doc@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org References: <20230915093649.435163-1-anshuman.khandual@arm.com> <20230915093649.435163-3-anshuman.khandual@arm.com> From: Anshuman Khandual In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/20/23 14:52, Suzuki K Poulose wrote: > On 15/09/2023 10:36, Anshuman Khandual wrote: >> Cycle counting is enabled, when requested and supported but with a default >> threshold value ETM_CYC_THRESHOLD_DEFAULT i.e 0x100 getting into TRCCCCTLR, >> representing the minimum interval between cycle count trace packets. > > minor nit: > > When Cycle counting is enabled, we use a default threshold value (0x100) for the instruction trace cycle counting. >> >> This makes cycle threshold user configurable, from the user space via perf >> event attributes. Although it falls back using ETM_CYC_THRESHOLD_DEFAULT, >> in case no explicit request. > > Minor nit: > > This patch makes the cycle threshold user configurable via perf event > attributes( 'cc_threshold' => event->attr.config3[11:0] ), falling back > to the the current default if unspecified. > > > >> As expected it creates a sysfs file as well. > > >> >> /sys/bus/event_source/devices/cs_etm/format/cc_threshold >> >> New 'cc_threshold' uses 'event->attr.config3' as no more space is available >> in 'event->attr.config1' or 'event->attr.config2'. > > Trim the above part. > > > Rest looks fine to me. Will change the commit message as follows. coresight: etm: Make cycle count threshold user configurable When cycle counting is enabled, we use a default threshold value i.e 0x100 for the instruction trace cycle counting. This patch makes the cycle threshold user configurable via perf event attributes( 'cc_threshold' => event->attr.config3[11:0] ), falling back to the current default if unspecified.