From: "Heiko Stübner" <heiko@sntech.de>
To: Christoph Hellwig <hch@lst.de>
Cc: palmer@dabbelt.com, paul.walmsley@sifive.com,
aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, wefu@redhat.com,
liush@allwinnertech.com, guoren@kernel.org,
atishp@atishpatra.org, anup@brainfault.org, drew@beagleboard.org,
hch@lst.de, arnd@arndb.de, wens@csie.org, maxime@cerno.tech,
gfavor@ventanamicro.com, andrea.mondelli@huawei.com,
behrensj@mit.edu, xinhaoqu@huawei.com, mick@ics.forth.gr,
allen.baum@esperantotech.com, jscheid@ventanamicro.com,
rtrauben@gmail.com, samuel@sholland.org, cmuellner@linux.com,
philipp.tomsich@vrull.eu, Atish Patra <atishp@rivosinc.com>
Subject: Re: [PATCH v8 01/14] riscv: prevent null-pointer dereference with sbi_remote_fence_i
Date: Thu, 31 Mar 2022 14:28:06 +0200 [thread overview]
Message-ID: <2260961.n0HT0TaD9V@diego> (raw)
In-Reply-To: <20220331095155.GA23422@lst.de>
Hi,
Am Donnerstag, 31. März 2022, 11:51:55 CEST schrieb Christoph Hellwig:
> On Thu, Mar 24, 2022 at 01:06:57AM +0100, Heiko Stuebner wrote:
> > The callback used inside sbi_remote_fence_i is set at sbi probe time
> > to the needed variant. Before that it is a NULL pointer.
> >
> > Some users like the flush_icache_*() functions suggest a generic
> > functionality, that doesn't depend on a specific boot-stage but
> > uses sbi_remote_fence_i as one option to flush other cpu cores.
> >
> > So they definitely shouldn't run into null-pointer dereference
> > issues when called "too early" during boot.
> >
> > So introduce an empty function to be the standard for the __sbi_rfence
> > function pointer until sbi_init has run.
> >
> > Users of sbi_remote_fence_i will have separate code for the local
> > cpu and sbi_init() is called before other cpus are brought up.
> > So there are no other cpus present at the time when the issue
> > might happen.
>
> I don't really understand this changelog. If flush_icache_* or
> other routines using SBI calls are called too early they won't
> do what they are asked to do, which implies a bug in the code.
>
> So crashing absolutely is the right thing to do here as we don't
> really have any other error reporting method available.
>
> So unless I'm totally misunderstanding what you are saying here:
>
> Nacked-by: Christoph Hellwig <hch@lst.de>
The function is defined as
void flush_icache_all(void)
{
local_flush_icache_all();
if (IS_ENABLED(CONFIG_RISCV_SBI))
sbi_remote_fence_i(NULL);
else
on_each_cpu(ipi_remote_fence_i, NULL, 1);
}
so essentially flushes the _local_ icache first and then tries to flush
caches on other cores, either via an ipi or via sbi.
The remote-fence callback is set correctly during sbi_init().
The other cores are only brought up after sbi-init is done.
So it's not really about error reporting but making sure that flush_icache_all()
does something sane even when still running on the first core.
As I assume the "all" means on all available cores (which would be the
core the system booted on).
Does this make it clearer what this tries to solve?
Heiko
next prev parent reply other threads:[~2022-03-31 12:28 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-24 0:06 [PATCH v8 00/14] riscv: support for Svpbmt and D1 memory types Heiko Stuebner
2022-03-24 0:06 ` [PATCH v8 01/14] riscv: prevent null-pointer dereference with sbi_remote_fence_i Heiko Stuebner
2022-03-31 9:51 ` Christoph Hellwig
2022-03-31 12:28 ` Heiko Stübner [this message]
2022-03-31 12:33 ` Christoph Hellwig
2022-04-07 18:50 ` Heiko Stübner
2022-03-24 0:06 ` [PATCH v8 02/14] riscv: integrate alternatives better into the main architecture Heiko Stuebner
2022-03-31 9:53 ` Christoph Hellwig
2022-03-24 0:06 ` [PATCH v8 03/14] riscv: allow different stages with alternatives Heiko Stuebner
2022-03-24 0:07 ` [PATCH v8 04/14] riscv: implement module alternatives Heiko Stuebner
2022-03-24 0:07 ` [PATCH v8 05/14] riscv: implement ALTERNATIVE_2 macro Heiko Stuebner
2022-03-31 9:56 ` Christoph Hellwig
2022-03-24 0:07 ` [PATCH v8 06/14] riscv: extend concatenated alternatives-lines to the same length Heiko Stuebner
2022-03-24 0:07 ` [PATCH v8 07/14] riscv: prevent compressed instructions in alternatives Heiko Stuebner
2022-03-31 9:56 ` Christoph Hellwig
2022-03-24 0:07 ` [PATCH v8 08/14] riscv: move boot alternatives to after fill_hwcap Heiko Stuebner
2022-03-31 9:57 ` Christoph Hellwig
2022-03-24 0:07 ` [PATCH v8 09/14] riscv: Fix accessing pfn bits in PTEs for non-32bit variants Heiko Stuebner
2022-03-31 9:59 ` Christoph Hellwig
2022-03-24 0:07 ` [PATCH v8 10/14] riscv: add cpufeature handling via alternatives Heiko Stuebner
2022-03-31 10:01 ` Christoph Hellwig
2022-04-08 16:13 ` Heiko Stübner
2022-03-24 0:07 ` [PATCH v8 11/14] riscv: add RISC-V Svpbmt extension support Heiko Stuebner
2022-03-31 10:03 ` Christoph Hellwig
2022-03-31 12:19 ` Heiko Stübner
2022-03-31 12:27 ` Christoph Hellwig
2022-03-31 12:29 ` Christoph Hellwig
2022-03-24 0:07 ` [PATCH v8 12/14] riscv: remove FIXMAP_PAGE_IO and fall back to its default value Heiko Stuebner
2022-03-31 10:03 ` Christoph Hellwig
2022-03-24 0:07 ` [PATCH v8 13/14] riscv: don't use global static vars to store alternative data Heiko Stuebner
2022-03-24 0:07 ` [PATCH v8 14/14] riscv: add memory-type errata for T-Head Heiko Stuebner
2022-03-31 2:24 ` [PATCH v8 00/14] riscv: support for Svpbmt and D1 memory types Palmer Dabbelt
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