From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC24A21360; Sun, 14 Apr 2024 07:51:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713081067; cv=none; b=QXnz6JwNhSsJAZIEfORzoAH7tT3w4H94oRWJ//llya+ZTESvwsXigOC/29ud6qTKiLqhmJW/4efzYLlnysL4qoeNMXZphLU+c4grDSd87f/3ExC3efHVoRzuHSsUJc9WUhjl1xlZkSVJon0iI/q+eWAerVkqtigimK1KWwiz2Wo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713081067; c=relaxed/simple; bh=6GuqLWvuYUqQo5TDZvw45mpK3aLhCABT5CnF056sszg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TtQeMhdINWYZ3ZsVB6rZ4G1OF1teJXegFgjZJAtbGnfwmQl+BwYveuEmygAaR4GbhYruQoRcPlUiq6YdUNhVCRxjp4swhQ9LULWY82D7wm/4Le/5AK/eZrw9RIwCVJoiGeb6tJkIhGEMWr9tbE0Qiy0g5sTHm6f+C6SgyWkorXw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Received: from i5e8616c3.versanet.de ([94.134.22.195] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1rvudE-0001KG-L5; Sun, 14 Apr 2024 09:50:32 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: soc@kernel.org, Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Dinh Nguyen , Tsahee Zidenberg , Antoine Tenart , Khuong Dinh , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Ray Jui , Scott Branden , Robert Richter , Shawn Guo , Li Yang , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , "Paul J. Murphy" , Daniele Alessandrelli , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Matthias Brugger , AngeloGioacchino Del Regno , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Konrad Dybcio , Andreas =?ISO-8859-1?Q?F=E4rber?= , Orson Zhai , Baolin Wang , Chunyan Zhang , Jisheng Zhang , Alim Akhtar , linux-fsd@tesla.com, Michal Simek , Rob Herring Cc: devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-mediatek@lists.infradead.org, linux-tegra@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-realtek-soc@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: Re: [PATCH] arm/arm64: dts: Drop "arm,armv8-pmuv3" compatible usage Date: Sun, 14 Apr 2024 09:50:29 +0200 Message-ID: <2262532.iZASKD2KPV@diego> In-Reply-To: <20240412222857.3873079-1-robh@kernel.org> References: <20240412222857.3873079-1-robh@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Am Samstag, 13. April 2024, 00:28:51 CEST schrieb Rob Herring: > The "arm,armv8-pmuv3" compatible is intended only for s/w models. Primarily, > it doesn't provide any detail on uarch specific events. > > There's still remaining cases for CPUs without any corresponding PMU > definition and for big.LITTLE systems which only have a single PMU node > (there should be one per core type). > > Signed-off-by: Rob Herring > --- > SoC Maintainers, Can you please apply this directly. > --- > arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 +- > diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi > index 62af0cb94839..734f87db4d11 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi > @@ -141,7 +141,7 @@ cpu_b3: cpu@103 { > }; > > arm-pmu { > - compatible = "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > interrupts = , > , > , For Rockchip: Acked-by: Heiko Stuebner