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Tue, 30 Sep 2025 05:37:21 -0700 (PDT) Message-ID: <22eb04cd1337f155c8c373db81d4e1a03380f395.camel@gmail.com> Subject: Re: [PATCH v2 4/6] iio: adc: ad4080: add support for AD4084 From: Nuno =?ISO-8859-1?Q?S=E1?= To: Antoniu Miclaus , jic23@kernel.org, robh@kernel.org, conor+dt@kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Date: Tue, 30 Sep 2025 13:37:48 +0100 In-Reply-To: <20250930103229.28696-4-antoniu.miclaus@analog.com> References: <20250930103229.28696-1-antoniu.miclaus@analog.com> <20250930103229.28696-4-antoniu.miclaus@analog.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2025-09-30 at 10:32 +0000, Antoniu Miclaus wrote: > Add support for AD4084 16-bit SAR ADC. The AD4084 differs from > AD4080 in resolution (16-bit vs 20-bit) and LVDS CNV clock count > maximum (2 vs 7). >=20 > Changes: > - Add AD4084_CHIP_ID definition (0x0054) > - Create ad4084_channel with 16-bit resolution and storage > - Add ad4084_chip_info with appropriate configuration > - Register AD4084 in device ID and OF match tables >=20 > Signed-off-by: Antoniu Miclaus > --- Reviewed-by: Nuno S=C3=A1 > no changes in v2. > =C2=A0drivers/iio/adc/ad4080.c | 15 +++++++++++++++ > =C2=A01 file changed, 15 insertions(+) >=20 > diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c > index fa15b8f63b8a..a68d7fa9f977 100644 > --- a/drivers/iio/adc/ad4080.c > +++ b/drivers/iio/adc/ad4080.c > @@ -126,6 +126,7 @@ > =C2=A0/* Miscellaneous Definitions */ > =C2=A0#define > AD4080_SPI_READ BIT(7) > =C2=A0#define AD4080_CHIP_ID 0x0050 > +#define AD4084_CHIP_ID 0x0054 > =C2=A0 > =C2=A0#define AD4080_LVDS_CNV_CLK_CNT_MAX 7 > =C2=A0 > @@ -435,6 +436,8 @@ static struct iio_chan_spec_ext_info ad4080_ext_info[= ] =3D { > =C2=A0 > =C2=A0static const struct iio_chan_spec ad4080_channel =3D AD4080_CHANNEL= _DEFINE(20, > 32); > =C2=A0 > +static const struct iio_chan_spec ad4084_channel =3D AD4080_CHANNEL_DEFI= NE(16, > 16); > + > =C2=A0static const struct ad4080_chip_info ad4080_chip_info =3D { > =C2=A0 .name =3D "ad4080", > =C2=A0 .product_id =3D AD4080_CHIP_ID, > @@ -445,6 +448,16 @@ static const struct ad4080_chip_info ad4080_chip_inf= o =3D { > =C2=A0 .lvds_cnv_clk_cnt_max =3D AD4080_LVDS_CNV_CLK_CNT_MAX, > =C2=A0}; > =C2=A0 > +static const struct ad4080_chip_info ad4084_chip_info =3D { > + .name =3D "ad4084", > + .product_id =3D AD4084_CHIP_ID, > + .scale_table =3D ad4080_scale_table, > + .num_scales =3D ARRAY_SIZE(ad4080_scale_table), > + .num_channels =3D 1, > + .channels =3D &ad4084_channel, > + .lvds_cnv_clk_cnt_max =3D 2, > +}; > + > =C2=A0static int ad4080_setup(struct iio_dev *indio_dev) > =C2=A0{ > =C2=A0 struct ad4080_state *st =3D iio_priv(indio_dev); > @@ -598,12 +611,14 @@ static int ad4080_probe(struct spi_device *spi) > =C2=A0 > =C2=A0static const struct spi_device_id ad4080_id[] =3D { > =C2=A0 { "ad4080", (kernel_ulong_t)&ad4080_chip_info }, > + { "ad4084", (kernel_ulong_t)&ad4084_chip_info }, > =C2=A0 { } > =C2=A0}; > =C2=A0MODULE_DEVICE_TABLE(spi, ad4080_id); > =C2=A0 > =C2=A0static const struct of_device_id ad4080_of_match[] =3D { > =C2=A0 { .compatible =3D "adi,ad4080", &ad4080_chip_info }, > + { .compatible =3D "adi,ad4084", &ad4084_chip_info }, > =C2=A0 { } > =C2=A0}; > =C2=A0MODULE_DEVICE_TABLE(of, ad4080_of_match);