From: Alexander Stein <alexander.stein@systec-electronic.com>
To: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Cc: Marc Zyngier <marc.zyngier@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [RFC] irqchip: add support for LS1021A external interrupt lines
Date: Mon, 11 Dec 2017 15:38:13 +0100 [thread overview]
Message-ID: <2302267.dSSx8ic0iv@ws-stein> (raw)
In-Reply-To: <7badefae-a952-7839-0bfe-dcd09ea1204f@prevas.dk>
On Monday, December 11, 2017, 3:06:52 PM CET Rasmus Villemoes wrote:
> On 2017-12-11 14:45, Rasmus Villemoes wrote:
> > On 2017-12-11 11:02, Alexander Stein wrote:
> >
> >> Oh, and what is the content of register SCFG_SCFGREVCR?
> >
> > Good point. On my board it's 0xffffffff, set even before U-boot starts,
> > and lots board support code in U-boot expects this. I can't immediately
> > find examples in the linux source code that actually writes to the scfg,
>
> Not a write, but we do already implicitly assume SCFG_SCFGREVCR is set
> to all-ones: In drivers/pci/dwc/pci-layerscape.c, bits which are
> numbered 6-11 in the reference manual are extracted with a regmap_read()
> followed by a left-shift by 20 and mask with 0x3f. That's consistent
> with me setting bit 0 (reference manual enumeration) using 1U<<31.
We set SCFG_SCFGREVCR to all-ones too, even before u-boot in rcw. Problem
is, this bit-reversal is only valid for SCFG. It's a shame, but at least add
a comment in the code you expect SCFG_SCFGREVCR as 0xffffffff.
Best regards,
Alexander
next prev parent reply other threads:[~2017-12-11 14:38 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-04 15:11 polarity inversion on LS1021a Rasmus Villemoes
2017-12-04 15:23 ` Marc Zyngier
2017-12-08 14:33 ` [RFC] irqchip: add support for LS1021A external interrupt lines Rasmus Villemoes
2017-12-08 15:11 ` Alexander Stein
2017-12-08 16:09 ` Marc Zyngier
2017-12-11 9:08 ` Rasmus Villemoes
2017-12-11 9:45 ` Alexander Stein
2017-12-11 10:02 ` Alexander Stein
2017-12-11 13:45 ` Rasmus Villemoes
2017-12-11 14:06 ` Rasmus Villemoes
2017-12-11 14:38 ` Alexander Stein [this message]
2017-12-08 16:02 ` Marc Zyngier
2017-12-11 9:30 ` Rasmus Villemoes
2017-12-11 18:29 ` Marc Zyngier
2017-12-12 23:28 ` Rob Herring
2017-12-15 22:55 ` Rasmus Villemoes
2017-12-21 22:45 ` Rob Herring
2017-12-20 8:30 ` [PATCH v2 1/2] irqchip: add support for Layerscape " Rasmus Villemoes
2017-12-20 8:30 ` [PATCH v2 2/2] dt/bindings: Add bindings for Layerscape external irqs Rasmus Villemoes
2017-12-21 22:44 ` Rob Herring
2018-01-22 9:21 ` [PATCH v3 1/2] irqchip: add support for Layerscape external interrupt lines Rasmus Villemoes
2018-01-22 9:21 ` [PATCH v3 2/2] dt/bindings: Add bindings for Layerscape external irqs Rasmus Villemoes
2018-01-24 15:28 ` Marc Zyngier
2018-01-25 15:02 ` [PATCH v4 1/2] irqchip: add support for Layerscape external interrupt lines Rasmus Villemoes
2018-01-25 15:02 ` [PATCH v4 2/2] dt/bindings: Add bindings for Layerscape external irqs Rasmus Villemoes
2018-02-05 6:07 ` Rob Herring
2018-02-08 15:08 ` Rasmus Villemoes
2018-02-09 9:47 ` Marc Zyngier
2018-02-23 21:08 ` [PATCH v5 0/2] irqchip: add support for Layerscape external interrupt lines Rasmus Villemoes
2018-02-23 21:08 ` [PATCH v5 1/2] " Rasmus Villemoes
2018-03-01 12:16 ` Thomas Gleixner
2018-05-04 7:44 ` Rasmus Villemoes
2019-09-17 9:39 ` Kurt Kanzenbach
2018-02-23 21:09 ` [PATCH v5 2/2] dt/bindings: Add bindings for Layerscape external irqs Rasmus Villemoes
2018-03-02 19:49 ` Rob Herring
2018-05-04 8:07 ` Rasmus Villemoes
2017-12-04 15:31 ` polarity inversion on LS1021a Alexander Stein
2017-12-04 15:37 ` Marc Zyngier
2017-12-04 16:04 ` Alexander Stein
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