From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6509B19309E; Wed, 10 Jul 2024 14:54:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720623259; cv=none; b=HkLIFq4GaKHMDLseO+OJtMZEBfCrJgg2N1BmQiu27BhjB3BEoCkgkl62AvJsB2uX1GQcKT3x69tlT7YnbQsrYdwn7YlNehIu3JNI+V3gNinz9HhFu7utkTyNL7moxKLuoVQ8E807BdkmxbPMy00lY05ZCVOceJ5Y38eRa+4yCX4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1720623259; c=relaxed/simple; bh=jtKNi88GuEEsD6lUfJjcFvJcOFXfvvWoyrmV2xC/5NY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JuMXpivuGFf+aYn2W+qf5gW0RYeHYh4NO3N4P1coqopjJLE7ChjFsUvfP+PYJJlmn4xajnbtWTmsCLNsyAAASC9VuLDxpbBPYotunpTJq1YZB8hQ1LKQu2pequVcuwlG1aQ6C8RrkSdCV6i7KO3LDvwsGR+nttUtTBuplWy/i7c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Received: from i5e860d18.versanet.de ([94.134.13.24] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1sRYhs-0001Wz-A6; Wed, 10 Jul 2024 16:54:08 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anand Moon Cc: Anand Moon , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1] arm64: dts: rockchip: Add missing pinctrl for PCIe30x4 node Date: Wed, 10 Jul 2024 16:54:07 +0200 Message-ID: <2356091.ECZNHGQPT7@diego> In-Reply-To: <20240710142001.7234-1-linux.amoon@gmail.com> References: <20240710142001.7234-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Hi, Am Mittwoch, 10. Juli 2024, 16:19:56 CEST schrieb Anand Moon: > Add missing pinctrl settings for PCIe 3.0 x4 clock request and wake > signals. Rename node from 'pcie3' to 'pcie30x4' to align with schematic > nomenclature. > > Signed-off-by: Anand Moon > --- > .../boot/dts/rockchip/rk3588-rock-5b.dts | 20 +++++++++++++------ > 1 file changed, 14 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts > index 2e7512676b7e..a9b55b7996cf 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts > @@ -301,7 +301,7 @@ &pcie30phy { > > &pcie3x4 { > pinctrl-names = "default"; > - pinctrl-0 = <&pcie3_rst>; > + pinctrl-0 = <&pcie30x4_perstn_m1 &pcie30x4_clkreqn_m1 &pcie30x4_waken_m1>; > reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; > vpcie3v3-supply = <&vcc3v3_pcie30>; > status = "okay"; > @@ -340,14 +340,22 @@ pcie2_2_rst: pcie2-2-rst { > }; > }; > > - pcie3 { > - pcie3_rst: pcie3-rst { > - rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; > - }; > - > + pcie30x4 { > pcie3_vcc3v3_en: pcie3-vcc3v3-en { > rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; > }; > + > + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { > + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; > + }; > + > + pcie30x4_waken_m1: pcie30x4-waken-m1 { > + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; > + }; > + > + pcie30x4_perstn_m1: pcie30x4-perstn-m1 { > + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; > + }; I'm not sure what you're going for here, but defining them as gpio makes them essentially unused? Shouldn't they go to the pcie controller? >From what I found for example The PERST# signal is used to indicate when the power supply is within its specified voltage tolerance and is stable. At least you'll need to explain more in the commit message. Heiko