From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753014AbdEPUOx (ORCPT ); Tue, 16 May 2017 16:14:53 -0400 Received: from mx1.redhat.com ([209.132.183.28]:38546 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752426AbdEPUOr (ORCPT ); Tue, 16 May 2017 16:14:47 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 2CD818123E Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx01.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=eric.auger@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 2CD818123E Subject: Re: [PATCH 2/2] PCI: Avoid bus reset for Cavium cn8xxx root ports. To: David Daney , Bjorn Helgaas , linux-pci@vger.kernel.org References: <20170516001736.4001-1-david.daney@cavium.com> <20170516001736.4001-3-david.daney@cavium.com> Cc: Jon Masters , Robert Richter , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org From: Auger Eric Message-ID: <235a9a51-df06-84af-4e5d-b6408ceb0b7d@redhat.com> Date: Tue, 16 May 2017 22:14:40 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <20170516001736.4001-3-david.daney@cavium.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.25]); Tue, 16 May 2017 20:14:47 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 16/05/2017 02:17, David Daney wrote: > Root ports of cn8xxx do not function after bus reset when used with > some e1000e and LSI HBA devices. Add a quirk to prevent bus reset on > these root ports. I understand the bus reset would work along with a variety of other child devices. I guess there is no way to be more accurate and forbid the bus reset only when incompatible child devices are found? > > Signed-off-by: David Daney > --- > drivers/pci/quirks.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c > index 085fb78..02cd847 100644 > --- a/drivers/pci/quirks.c > +++ b/drivers/pci/quirks.c > @@ -3347,6 +3347,14 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); > DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); > DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); > > +/* > + * Root port on some Cavium CN8xxx chips do not successfully complete > + * a bus reset when used with certain types child devices. Config s/types /types of Thanks Eric > + * space access to the child may quit responding. Flag the root port > + * as not supporting bus reset. > + */ > +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); > + > static void quirk_no_pm_reset(struct pci_dev *dev) > { > /* >