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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDEzMDA4MyBTYWx0ZWRfX4+l2u4pG5hKa dJG2SJ5pWokyic81BzoSYnMHiBu0OCXTWtFNSEjUMeGQhE+7FN9l1sQViMCwH0qgqOc2wWXXm5N D6c0R/FZ8WPdCbwDBxlilZOznarkg470hEqFJ+yq0rAed/c/XH74OCiQbhtmjTijThN+RN7/Ejv EDILW0DCGP3ebZ+MuUi9n3MOvEcVRVDkQyECUhZszFro7mukc1fuedLClR8NLEOcBj4vcEXB0/Q KyEA+UZAk9EhGUPmurdpHLmF7pDzcSJ9q+NsqdQDXmQzcshuqnIopss70UzgW1LeKI0+UTaNNUr PYQlfBkGh02dmQrKFNtDWhUkHL0QpWyq3GV67r8LXQWLRiNkeRGYaew/fLdy8GOZ6WPWIO6PuqE KqeZlrah67PHHODj4nLqvzZ3EMD7Cg== X-Authority-Analysis: v=2.4 cv=Fr4IPmrq c=1 sm=1 tr=0 ts=68ef7756 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=5RRmG2Rm61FAXBKOsCEA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-GUID: 1g_4yNCwEZWIc71yDXj5Os62HQzpaAjX X-Proofpoint-ORIG-GUID: 1g_4yNCwEZWIc71yDXj5Os62HQzpaAjX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-15_04,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 spamscore=0 phishscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510130083 On 9/25/2025 3:48 PM, Konrad Dybcio wrote: > On 9/25/25 8:32 AM, Pankaj Patil wrote: >> From: Jyothi Kumar Seerapu >> >> Add device tree support for QUPv3 serial engine protocols on Glymur. >> Glymur has 24 QUP serial engines across 3 QUP wrappers, each with >> support of GPI DMA engines. >> >> Signed-off-by: Jyothi Kumar Seerapu >> Signed-off-by: Pankaj Patil >> --- > > [...] > >> + gpi_dma2: dma-controller@800000 { >> + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; >> + reg = <0 0x00800000 0 0x60000>; >> + interrupts = , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + , >> + ; >> + dma-channels = <16>; >> + dma-channel-mask = <0x3f>; >> + #dma-cells = <3>; >> + iommus = <&apps_smmu 0xd76 0x0>; >> + status = "ok"; > > this is implied by default, drop Hi Konard, Do you mean we should remove the status property for all QUPs and GPI_DMAs from the common device tree (SOC) and enable them only in the board-specific device tree files? > >> + }; >> + >> qupv3_2: geniqup@8c0000 { >> compatible = "qcom,geni-se-qup"; >> reg = <0x0 0x008c0000 0x0 0x3000>; >> @@ -718,6 +744,339 @@ qupv3_2: geniqup@8c0000 { >> #address-cells = <2>; >> #size-cells = <2>; >> ranges; >> + status = "ok"; > > ditto > > (please resolve all occurences) > > [...] > >> + cnoc_main: interconnect@1500000 { >> + compatible = "qcom,glymur-cnoc-main"; >> + reg = <0x0 0x01500000 0x0 0x17080>; >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + #interconnect-cells = <2>; >> + }; >> + >> + config_noc: interconnect@1600000 { >> + compatible = "qcom,glymur-cnoc-cfg"; >> + reg = <0x0 0x01600000 0x0 0x6600>; >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + #interconnect-cells = <2>; >> + }; >> + >> + system_noc: interconnect@1680000 { >> + compatible = "qcom,glymur-system-noc"; >> + reg = <0x0 0x01680000 0x0 0x1c080>; >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + #interconnect-cells = <2>; >> + }; > > This diff becomes unreadable really fast.. please play with git > format-patch's --patience option > > Konrad