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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38f258f5efdsm21016778f8f.43.2025.02.20.10.12.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2025 10:12:45 -0800 (PST) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Emilio =?UTF-8?B?TMOzcGV6?= , David Laight , Anastasia Belova Cc: Anastasia Belova , Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Samuel Holland , Maxime Ripard , Hans de Goede , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, lvc-project@linuxtesting.org Subject: Re: [PATCH] clk: sunxi: clean up rate counting Date: Thu, 20 Feb 2025 19:12:43 +0100 Message-ID: <2385242.n0HT0TaD9V@jernej-laptop> In-Reply-To: <20250203112930.650813-1-abelova@astralinux.ru> References: <20250203112930.650813-1-abelova@astralinux.ru> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne ponedeljek, 3. februar 2025 ob 12:29:28 Srednjeevropski standardni =C4= =8Das je Anastasia Belova napisal(a): > If n =3D 255, the result of multiplication of n and 24000000 > may not fit int type. Swap division and shift with multiplication. >=20 > Found by Linux Verification Center (linuxtesting.org) with SVACE. >=20 > Fixes: 6424e0aeebc4 ("clk: sunxi: rewrite sun9i_a80_get_pll4_factors()") > Signed-off-by: Anastasia Belova While this should work, should we try to remove (old) sunxi clock drivers instead? Drivers we converted 8 years ago, except A20 GMAC and A80 PRCM clo= cks. Even if we convert them now, we need some transition time for them. Best regards, Jernej > --- > drivers/clk/sunxi/clk-sun9i-core.c | 14 +++++++++----- > 1 file changed, 9 insertions(+), 5 deletions(-) >=20 > diff --git a/drivers/clk/sunxi/clk-sun9i-core.c b/drivers/clk/sunxi/clk-s= un9i-core.c > index d93c7a53c6c0..639c83ed63b8 100644 > --- a/drivers/clk/sunxi/clk-sun9i-core.c > +++ b/drivers/clk/sunxi/clk-sun9i-core.c > @@ -25,12 +25,12 @@ > =20 > static void sun9i_a80_get_pll4_factors(struct factors_request *req) > { > - int n; > - int m =3D 1; > - int p =3D 1; > + unsigned int n; > + unsigned int m =3D 1; > + unsigned int p =3D 1; > =20 > /* Normalize value to a 6 MHz multiple (24 MHz / 4) */ > - n =3D DIV_ROUND_UP(req->rate, 6000000); > + n =3D DIV_ROUND_UP(req->rate, 6000000ul); > =20 > /* If n is too large switch to steps of 12 MHz */ > if (n > 255) { > @@ -50,7 +50,11 @@ static void sun9i_a80_get_pll4_factors(struct factors_= request *req) > else if (n < 12) > n =3D 12; > =20 > - req->rate =3D ((24000000 * n) >> p) / (m + 1); > + /* Division and shift should be done before multiplication to > + * avoid overflow. The result will be correct because '>> p' and > + * '/ (m + 1)' are both just conditional 'divide by 2' > + */ > + req->rate =3D ((24000000ul >> p) / (m + 1)) * n; > req->n =3D n; > req->m =3D m; > req->p =3D p; >=20