From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4C270C54EBC for ; Wed, 11 Jan 2023 23:30:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236029AbjAKXaK (ORCPT ); Wed, 11 Jan 2023 18:30:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231620AbjAKXaG (ORCPT ); Wed, 11 Jan 2023 18:30:06 -0500 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07EABB97; Wed, 11 Jan 2023 15:30:03 -0800 (PST) Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1pFkXe-00019a-Nt; Thu, 12 Jan 2023 00:29:58 +0100 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , Jisheng Zhang Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Andrew Jones Subject: Re: [PATCH v3 05/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Date: Thu, 12 Jan 2023 00:29:57 +0100 Message-ID: <2398293.3Lj2Plt8kZ@diego> In-Reply-To: <20230111171027.2392-6-jszhang@kernel.org> References: <20230111171027.2392-1-jszhang@kernel.org> <20230111171027.2392-6-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jisheng. Am Mittwoch, 11. Januar 2023, 18:10:19 CET schrieb Jisheng Zhang: > riscv_cpufeature_patch_func() currently only scans a limited set of > cpufeatures, explicitly defined with macros. Extend it to probe for all > ISA extensions. > > Signed-off-by: Jisheng Zhang > Reviewed-by: Andrew Jones > Reviewed-by: Heiko Stuebner > --- > arch/riscv/include/asm/errata_list.h | 9 ++-- > arch/riscv/kernel/cpufeature.c | 63 ++++------------------------ > 2 files changed, 11 insertions(+), 61 deletions(-) hmmm ... I do see a somewhat big caveat for this. and would like to take back my Reviewed-by for now With this change we would limit the patchable cpufeatures to actual riscv extensions. But cpufeatures can also be soft features like how performant the core handles unaligned accesses. See Palmer's series [0]. Also this essentially codifies that each ALTERNATIVE can only ever be attached to exactly one extension. But contrary to vendor-errata, it is very likely that we will need combinations of different extensions for some alternatives in the future. In my optimization quest, I found that it's actually pretty neat to convert the errata-id for cpufeatures to a bitfield [1], because then it's possible to just combine extensions into said bitfield [2]: ALTERNATIVE_2("nop", "j strcmp_zbb_unaligned", 0, CPUFEATURE_ZBB | CPUFEATURE_FAST_UNALIGNED, 0, CONFIG_RISCV_ISA_ZBB, "j variant_zbb", 0, CPUFEATURE_ZBB, CPUFEATURE_FAST_UNALIGNED, CONFIG_RISCV_ISA_ZBB) [the additional field there models a "not" component] So I really feel this would limit us quite a bit. Heiko [0] https://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git/commit/?h=riscv-hwprobe-v1&id=510c491cb9d87dcbdc91c63558dc704968723240 [1] https://github.com/mmind/linux-riscv/commit/f57a896122ee7e666692079320fc35829434cf96 [2] https://github.com/mmind/linux-riscv/commit/8cef615dab0c00ad68af2651ee5b93d06be17f27#diff-194cb8a86f9fb9b03683295f21c8f46b456a9f94737f01726ddbcbb9e3aace2cR12