Re: [PATCH net-next v3 1/3] net: phy: qcom: Add PHY counter support

[Luo Jie <quic_luoj@quicinc.com>]

On 7/16/2025 12:11 AM, Andrew Lunn wrote:
>> +int qcom_phy_update_stats(struct phy_device *phydev,
>> +			  struct qcom_phy_hw_stats *hw_stats)
>> +{
>> +	int ret;
>> +	u32 cnt;
>> +
>> +	/* PHY 32-bit counter for RX packets. */
>> +	ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_RX_PKT_15_0);
>> +	if (ret < 0)
>> +		return ret;
>> +
>> +	cnt = ret;
>> +
>> +	ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_RX_PKT_31_16);
>> +	if (ret < 0)
>> +		return ret;
> 
> Does reading QCA808X_MMD7_CNT_RX_PKT_15_0 cause
> QCA808X_MMD7_CNT_RX_PKT_31_16 to latch?

Checked with the hardware design team: The high 16-bit counter register
does not latch when reading the low 16 bits.

> 
> Sometimes you need to read the high part, the low part, and then
> reread the high part to ensure it has not incremented. But this is
> only needed if the hardware does not latch.
> 
> 	Andrew

Since the counter is configured to clear after reading, the clear action
takes priority over latching the count. This means that when reading the
low 16 bits, the high 16-bit counter value cannot increment, any new
packet events occurring during the read will be recorded after the
16-bit counter is cleared.

Therefore, the current sequence for reading the counter is correct and
will not result in missed increments.