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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , , , References: <20250715-qcom_phy_counter-v3-0-8b0e460a527b@quicinc.com> <20250715-qcom_phy_counter-v3-1-8b0e460a527b@quicinc.com> Content-Language: en-US From: Luo Jie In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: M5X2zcMiwn-irENWv7xRaP0a71Xn4O9p X-Proofpoint-ORIG-GUID: M5X2zcMiwn-irENWv7xRaP0a71Xn4O9p X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE2MDA5MSBTYWx0ZWRfX1/T8Q/bRrCk6 0mXZ4Rv8xbbR65tp19tFb+Ycay/IdxXf/0JAbfCZoYoG58SNFYRMQ8z8d65MvsEWrDIz5x5q0xC W1Tq8djecVAvhxuzVL4HISGs7IYtMH3uiYSRmIhcWW1R5BTRp0gDH0G7/Su7pYM+lBoNk/Y/OJk 9kjAGegEeReFdDStIaig8dqXR1+prKKOxzT4KQPLCO8d7BaljJRSreVh/AR4yawSCGle2MoHysA uDzARWvy0OxvTvQ3EaZW2yGuWrSAxvAecrhyQdg3j+pm1TU59WsvtOLoojQFv5liBkbJwT8tv2U ufE7yBkg/uxOeAk1HB23RnITdPPNFlcicI9+9rtlGGrdPYlitQ8Q4WqsPe6wwqcOk2HCW2gr8Uz sZ2HWEINvAjUcSSU1SBkcbT7RpUmbVxfxKOVUYlbQP/0Jg+Xjs2t6sbCq3DxH06XVO+foaAH X-Authority-Analysis: v=2.4 cv=Xc2JzJ55 c=1 sm=1 tr=0 ts=68777bb4 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=dx8Nv9QYUwUAvIcoxGYA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-16_01,2025-07-15_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 priorityscore=1501 adultscore=0 mlxlogscore=999 phishscore=0 suspectscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507160091 On 7/16/2025 12:11 AM, Andrew Lunn wrote: >> +int qcom_phy_update_stats(struct phy_device *phydev, >> + struct qcom_phy_hw_stats *hw_stats) >> +{ >> + int ret; >> + u32 cnt; >> + >> + /* PHY 32-bit counter for RX packets. */ >> + ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_RX_PKT_15_0); >> + if (ret < 0) >> + return ret; >> + >> + cnt = ret; >> + >> + ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_RX_PKT_31_16); >> + if (ret < 0) >> + return ret; > > Does reading QCA808X_MMD7_CNT_RX_PKT_15_0 cause > QCA808X_MMD7_CNT_RX_PKT_31_16 to latch? Checked with the hardware design team: The high 16-bit counter register does not latch when reading the low 16 bits. > > Sometimes you need to read the high part, the low part, and then > reread the high part to ensure it has not incremented. But this is > only needed if the hardware does not latch. > > Andrew Since the counter is configured to clear after reading, the clear action takes priority over latching the count. This means that when reading the low 16 bits, the high 16-bit counter value cannot increment, any new packet events occurring during the read will be recorded after the 16-bit counter is cleared. Therefore, the current sequence for reading the counter is correct and will not result in missed increments.