* Re: [PATCH v2] arm64: dts: ti: k3-am64* Disable ethernet by default at SoC level
2024-08-09 13:57 [PATCH v2] arm64: dts: ti: k3-am64* Disable ethernet by default at SoC level Logan Bristol
@ 2024-08-25 11:18 ` Josua Mayer
2024-08-26 21:12 ` Logan Bristol
2024-08-26 5:29 ` Daniel Schultz
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Josua Mayer @ 2024-08-25 11:18 UTC (permalink / raw)
To: Logan Bristol, Krzysztof Kozlowski, Conor Dooley,
Vignesh Raghavendra, Nishanth Menon
Cc: Matt McKee, Wadim Egorov, linux@ew.tq-group.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Hi Logan,
Tank you for incorporating the requested changes,
unfortunately I found another mistake ... see below.
Am 09.08.24 um 16:57 schrieb Logan Bristol:
> External interfaces should be disabled at the SoC DTSI level, since
> the node is incomplete. Disable Ethernet switch and ports in SoC DTSI
> and enable them in the board DTS. If the board DTS includes a SoM DTSI
> that completes the node description, enable the Ethernet switch and ports
> in SoM DTSI.
>
> Reflect this change in SoM DTSIs by removing ethernet port disable.
>
> Signed-off-by: Logan Bristol <logan.bristol@utexas.edu>
> ---
> Changes since v1:
> - Enabled cpsw3g and cpsw_port1 in SoM DTSI instead of board DTS
> if board DTS included SoM DTSI
> ---
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 3 +++
> arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 6 ++----
> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 3 +++
> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 3 +++
> arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 6 ++----
> arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 6 ++----
> 6 files changed, 15 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> index f8370dd03350..69c5af58b727 100644
> --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> @@ -677,6 +677,7 @@ cpsw3g: ethernet@8000000 {
> assigned-clock-parents = <&k3_clks 13 9>;
> clock-names = "fck";
> power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
> + status = "disabled";
>
> dmas = <&main_pktdma 0xC500 15>,
> <&main_pktdma 0xC501 15>,
> @@ -701,6 +702,7 @@ cpsw_port1: port@1 {
> phys = <&phy_gmii_sel 1>;
> mac-address = [00 00 00 00 00 00];
> ti,syscon-efuse = <&main_conf 0x200>;
> + status = "disabled";
> };
>
> cpsw_port2: port@2 {
> @@ -709,6 +711,7 @@ cpsw_port2: port@2 {
> label = "port2";
> phys = <&phy_gmii_sel 2>;
> mac-address = [00 00 00 00 00 00];
> + status = "disabled";
> };
> };
>
...
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
> index c19d0b8bbf0f..a5cec9a07510 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
> @@ -177,6 +177,7 @@ vdd_mmc0: regulator-vdd-mmc0 {
> &cpsw3g {
> pinctrl-names = "default";
> pinctrl-0 = <&rgmii1_default_pins>;
> + status = "okay";
correct
> };
>
> &cpsw3g_mdio {
> @@ -210,10 +211,7 @@ ethernet_phy0: ethernet-phy@0 {
> &cpsw_port1 {
> phy-mode = "rgmii-id";
> phy-handle = <ðernet_phy0>;
We use this port on the SoM, please set status okay.
> -};
> -
> -&cpsw_port2 {
> - status = "disabled";
> + status = "okay";
We are not using this port on the SoM, drop node to keep status disabled.
> };
>
> &icssg1_mdio {
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v2] arm64: dts: ti: k3-am64* Disable ethernet by default at SoC level
2024-08-25 11:18 ` Josua Mayer
@ 2024-08-26 21:12 ` Logan Bristol
2024-08-27 8:00 ` Josua Mayer
0 siblings, 1 reply; 9+ messages in thread
From: Logan Bristol @ 2024-08-26 21:12 UTC (permalink / raw)
To: Josua Mayer, Krzysztof Kozlowski, Conor Dooley,
Vignesh Raghavendra, Nishanth Menon
Cc: Matt McKee, Wadim Egorov, linux@ew.tq-group.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Hi Josua,
On 8/25/2024 6:18 AM, Josua Mayer wrote:
> Hi Logan,
>
> Tank you for incorporating the requested changes,
> unfortunately I found another mistake ... see below.
>
> Am 09.08.24 um 16:57 schrieb Logan Bristol:
>> External interfaces should be disabled at the SoC DTSI level, since
>> the node is incomplete. Disable Ethernet switch and ports in SoC DTSI
>> and enable them in the board DTS. If the board DTS includes a SoM DTSI
>> that completes the node description, enable the Ethernet switch and ports
>> in SoM DTSI.
>>
>> Reflect this change in SoM DTSIs by removing ethernet port disable.
>>
>> Signed-off-by: Logan Bristol <logan.bristol@utexas.edu>
>> ---
>> Changes since v1:
>> - Enabled cpsw3g and cpsw_port1 in SoM DTSI instead of board DTS
>> if board DTS included SoM DTSI
>> ---
>> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 3 +++
>> arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 6 ++----
>> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 3 +++
>> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 3 +++
>> arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 6 ++----
>> arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 6 ++----
>> 6 files changed, 15 insertions(+), 12 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>> index f8370dd03350..69c5af58b727 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>> @@ -677,6 +677,7 @@ cpsw3g: ethernet@8000000 {
>> assigned-clock-parents = <&k3_clks 13 9>;
>> clock-names = "fck";
>> power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
>> + status = "disabled";
>>
>> dmas = <&main_pktdma 0xC500 15>,
>> <&main_pktdma 0xC501 15>,
>> @@ -701,6 +702,7 @@ cpsw_port1: port@1 {
>> phys = <&phy_gmii_sel 1>;
>> mac-address = [00 00 00 00 00 00];
>> ti,syscon-efuse = <&main_conf 0x200>;
>> + status = "disabled";
>> };
>>
>> cpsw_port2: port@2 {
>> @@ -709,6 +711,7 @@ cpsw_port2: port@2 {
>> label = "port2";
>> phys = <&phy_gmii_sel 2>;
>> mac-address = [00 00 00 00 00 00];
>> + status = "disabled";
>> };
>> };
>>
> ...
>> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
>> index c19d0b8bbf0f..a5cec9a07510 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
>> @@ -177,6 +177,7 @@ vdd_mmc0: regulator-vdd-mmc0 {
>> &cpsw3g {
>> pinctrl-names = "default";
>> pinctrl-0 = <&rgmii1_default_pins>;
>> + status = "okay";
> correct
>> };
>>
>> &cpsw3g_mdio {
>> @@ -210,10 +211,7 @@ ethernet_phy0: ethernet-phy@0 {
>> &cpsw_port1 {
>> phy-mode = "rgmii-id";
>> phy-handle = <ðernet_phy0>;
> We use this port on the SoM, please set status okay.
>> -};
>> -
>> -&cpsw_port2 {
>> - status = "disabled";
>> + status = "okay";
> We are not using this port on the SoM, drop node to keep status disabled.
My understanding is that the cpsw_port1 node should be enabled and the
cpsw_port2 node should not exist in this DTSI. If my understanding is
correct, isn't that shown in this diff?
Thank you,
Logan Bristol
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v2] arm64: dts: ti: k3-am64* Disable ethernet by default at SoC level
2024-08-26 21:12 ` Logan Bristol
@ 2024-08-27 8:00 ` Josua Mayer
0 siblings, 0 replies; 9+ messages in thread
From: Josua Mayer @ 2024-08-27 8:00 UTC (permalink / raw)
To: Logan Bristol, Krzysztof Kozlowski, Conor Dooley,
Vignesh Raghavendra, Nishanth Menon
Cc: Matt McKee, Wadim Egorov, linux@ew.tq-group.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Am 27.08.24 um 00:12 schrieb Logan Bristol:
> Hi Josua,
>
> On 8/25/2024 6:18 AM, Josua Mayer wrote:
>> Hi Logan,
>>
>> Tank you for incorporating the requested changes,
>> unfortunately I found another mistake ... see below.
>>
>> Am 09.08.24 um 16:57 schrieb Logan Bristol:
>>> External interfaces should be disabled at the SoC DTSI level, since
>>> the node is incomplete. Disable Ethernet switch and ports in SoC DTSI
>>> and enable them in the board DTS. If the board DTS includes a SoM DTSI
>>> that completes the node description, enable the Ethernet switch and
>>> ports
>>> in SoM DTSI.
>>>
>>> Reflect this change in SoM DTSIs by removing ethernet port disable.
>>>
>>> Signed-off-by: Logan Bristol <logan.bristol@utexas.edu>
>>> ---
>>> Changes since v1:
>>> - Enabled cpsw3g and cpsw_port1 in SoM DTSI instead of board DTS
>>> if board DTS included SoM DTSI
>>> ---
>>> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 3 +++
>>> arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 6 ++----
>>> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 3 +++
>>> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 3 +++
>>> arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 6 ++----
>>> arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 6 ++----
>>> 6 files changed, 15 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>>> b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>>> index f8370dd03350..69c5af58b727 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>>> @@ -677,6 +677,7 @@ cpsw3g: ethernet@8000000 {
>>> assigned-clock-parents = <&k3_clks 13 9>;
>>> clock-names = "fck";
>>> power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
>>> + status = "disabled";
>>> dmas = <&main_pktdma 0xC500 15>,
>>> <&main_pktdma 0xC501 15>,
>>> @@ -701,6 +702,7 @@ cpsw_port1: port@1 {
>>> phys = <&phy_gmii_sel 1>;
>>> mac-address = [00 00 00 00 00 00];
>>> ti,syscon-efuse = <&main_conf 0x200>;
>>> + status = "disabled";
>>> };
>>> cpsw_port2: port@2 {
>>> @@ -709,6 +711,7 @@ cpsw_port2: port@2 {
>>> label = "port2";
>>> phys = <&phy_gmii_sel 2>;
>>> mac-address = [00 00 00 00 00 00];
>>> + status = "disabled";
>>> };
>>> };
>> ...
>>> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
>>> b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
>>> index c19d0b8bbf0f..a5cec9a07510 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
>>> @@ -177,6 +177,7 @@ vdd_mmc0: regulator-vdd-mmc0 {
>>> &cpsw3g {
>>> pinctrl-names = "default";
>>> pinctrl-0 = <&rgmii1_default_pins>;
>>> + status = "okay";
>> correct
>>> };
>>> &cpsw3g_mdio {
>>> @@ -210,10 +211,7 @@ ethernet_phy0: ethernet-phy@0 {
>>> &cpsw_port1 {
>>> phy-mode = "rgmii-id";
>>> phy-handle = <ðernet_phy0>;
>> We use this port on the SoM, please set status okay.
>>> -};
>>> -
>>> -&cpsw_port2 {
>>> - status = "disabled";
>>> + status = "okay";
>> We are not using this port on the SoM, drop node to keep status
>> disabled.
>
> My understanding is that the cpsw_port1 node should be enabled and the
> cpsw_port2 node should not exist in this DTSI. If my understanding is
> correct, isn't that shown in this diff?
You are right, sorry about that ... my eyes missed the minuses :(
Acked-By: Josua Mayer <josua@solid-run.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] arm64: dts: ti: k3-am64* Disable ethernet by default at SoC level
2024-08-09 13:57 [PATCH v2] arm64: dts: ti: k3-am64* Disable ethernet by default at SoC level Logan Bristol
2024-08-25 11:18 ` Josua Mayer
@ 2024-08-26 5:29 ` Daniel Schultz
2024-08-26 21:17 ` Logan Bristol
2024-08-27 9:26 ` Matthias Schiffer
2024-08-28 18:41 ` Nishanth Menon
3 siblings, 1 reply; 9+ messages in thread
From: Daniel Schultz @ 2024-08-26 5:29 UTC (permalink / raw)
To: Logan Bristol
Cc: Josua Mayer, Wadim Egorov, linux, devicetree, linux-kernel,
linux-arm-kernel, Conor Dooley, Krzysztof Kozlowski,
Vignesh Raghavendra, Nishanth Menon
Hey Logan,
my feedback is similar to Josua's.
On 09.08.24 15:57, Logan Bristol wrote:
> External interfaces should be disabled at the SoC DTSI level, since
> the node is incomplete. Disable Ethernet switch and ports in SoC DTSI
> and enable them in the board DTS. If the board DTS includes a SoM DTSI
> that completes the node description, enable the Ethernet switch and ports
> in SoM DTSI.
>
> Reflect this change in SoM DTSIs by removing ethernet port disable.
>
> Signed-off-by: Logan Bristol <logan.bristol@utexas.edu>
> ---
> Changes since v1:
> - Enabled cpsw3g and cpsw_port1 in SoM DTSI instead of board DTS
> if board DTS included SoM DTSI
> ---
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 3 +++
> arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 6 ++----
> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 3 +++
> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 3 +++
> arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 6 ++----
> arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 6 ++----
> 6 files changed, 15 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> index f8370dd03350..69c5af58b727 100644
> --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> @@ -677,6 +677,7 @@ cpsw3g: ethernet@8000000 {
> assigned-clock-parents = <&k3_clks 13 9>;
> clock-names = "fck";
> power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
> + status = "disabled";
>
> dmas = <&main_pktdma 0xC500 15>,
> <&main_pktdma 0xC501 15>,
> @@ -701,6 +702,7 @@ cpsw_port1: port@1 {
> phys = <&phy_gmii_sel 1>;
> mac-address = [00 00 00 00 00 00];
> ti,syscon-efuse = <&main_conf 0x200>;
> + status = "disabled";
> };
>
> cpsw_port2: port@2 {
> @@ -709,6 +711,7 @@ cpsw_port2: port@2 {
> label = "port2";
> phys = <&phy_gmii_sel 2>;
> mac-address = [00 00 00 00 00 00];
> + status = "disabled";
> };
> };
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
> index ea7c58fb67e2..6bece2fb4e95 100644
> --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
> @@ -185,6 +185,7 @@ AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* (C19) EXTINTn.GPIO1_70 */
> &cpsw3g {
> pinctrl-names = "default";
> pinctrl-0 = <&cpsw_rgmii1_pins_default>;
> + status = "okay";
> };
>
> &cpsw3g_mdio {
> @@ -208,10 +209,7 @@ cpsw3g_phy1: ethernet-phy@1 {
> &cpsw_port1 {
> phy-mode = "rgmii-rxid";
> phy-handle = <&cpsw3g_phy1>;
The connected phy is located on the SOM and should be enabled by default.
> -};
> -
> -&cpsw_port2 {
> - status = "disabled";
> + status = "okay";
> };
This port is routed to the carrier-board. Please drop this node.
Regards,
Daniel
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v2] arm64: dts: ti: k3-am64* Disable ethernet by default at SoC level
2024-08-26 5:29 ` Daniel Schultz
@ 2024-08-26 21:17 ` Logan Bristol
2024-08-29 5:49 ` Daniel Schultz
0 siblings, 1 reply; 9+ messages in thread
From: Logan Bristol @ 2024-08-26 21:17 UTC (permalink / raw)
To: Daniel Schultz
Cc: Josua Mayer, Wadim Egorov, linux, devicetree, linux-kernel,
linux-arm-kernel, Conor Dooley, Krzysztof Kozlowski,
Vignesh Raghavendra, Nishanth Menon
Hi Daniel,
On 8/26/2024 12:29 AM, Daniel Schultz wrote:
> Hey Logan,
>
> my feedback is similar to Josua's.
>
> On 09.08.24 15:57, Logan Bristol wrote:
>> External interfaces should be disabled at the SoC DTSI level, since
>> the node is incomplete. Disable Ethernet switch and ports in SoC DTSI
>> and enable them in the board DTS. If the board DTS includes a SoM DTSI
>> that completes the node description, enable the Ethernet switch and ports
>> in SoM DTSI.
>>
>> Reflect this change in SoM DTSIs by removing ethernet port disable.
>>
>> Signed-off-by: Logan Bristol <logan.bristol@utexas.edu>
>> ---
>> Changes since v1:
>> - Enabled cpsw3g and cpsw_port1 in SoM DTSI instead of board DTS
>> if board DTS included SoM DTSI
>> ---
>> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 3 +++
>> arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 6 ++----
>> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 3 +++
>> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 3 +++
>> arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 6 ++----
>> arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 6 ++----
>> 6 files changed, 15 insertions(+), 12 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/
>> boot/dts/ti/k3-am64-main.dtsi
>> index f8370dd03350..69c5af58b727 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>> @@ -677,6 +677,7 @@ cpsw3g: ethernet@8000000 {
>> assigned-clock-parents = <&k3_clks 13 9>;
>> clock-names = "fck";
>> power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
>> + status = "disabled";
>> dmas = <&main_pktdma 0xC500 15>,
>> <&main_pktdma 0xC501 15>,
>> @@ -701,6 +702,7 @@ cpsw_port1: port@1 {
>> phys = <&phy_gmii_sel 1>;
>> mac-address = [00 00 00 00 00 00];
>> ti,syscon-efuse = <&main_conf 0x200>;
>> + status = "disabled";
>> };
>> cpsw_port2: port@2 {
>> @@ -709,6 +711,7 @@ cpsw_port2: port@2 {
>> label = "port2";
>> phys = <&phy_gmii_sel 2>;
>> mac-address = [00 00 00 00 00 00];
>> + status = "disabled";
>> };
>> };
>> diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/
>> arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
>> index ea7c58fb67e2..6bece2fb4e95 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
>> @@ -185,6 +185,7 @@ AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* (C19)
>> EXTINTn.GPIO1_70 */
>> &cpsw3g {
>> pinctrl-names = "default";
>> pinctrl-0 = <&cpsw_rgmii1_pins_default>;
>> + status = "okay";
>> };
>> &cpsw3g_mdio {
>> @@ -208,10 +209,7 @@ cpsw3g_phy1: ethernet-phy@1 {
>> &cpsw_port1 {
>> phy-mode = "rgmii-rxid";
>> phy-handle = <&cpsw3g_phy1>;
> The connected phy is located on the SOM and should be enabled by default.
>> -};
>> -
>> -&cpsw_port2 {
>> - status = "disabled";
>> + status = "okay";
>> };
>
> This port is routed to the carrier-board. Please drop this node.
I replied similarly to Josua's comments, but if cpsw_port1 is to be
enabled and cpsw_port2 should be dropped from this DTSI, isn't that
shown in this diff?
Thank you,
Logan Bristol
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v2] arm64: dts: ti: k3-am64* Disable ethernet by default at SoC level
2024-08-26 21:17 ` Logan Bristol
@ 2024-08-29 5:49 ` Daniel Schultz
0 siblings, 0 replies; 9+ messages in thread
From: Daniel Schultz @ 2024-08-29 5:49 UTC (permalink / raw)
To: Logan Bristol
Cc: Josua Mayer, Wadim Egorov, linux, devicetree, linux-kernel,
linux-arm-kernel, Conor Dooley, Krzysztof Kozlowski,
Vignesh Raghavendra, Nishanth Menon
On 26.08.24 23:17, Logan Bristol wrote:
> Hi Daniel,
>
> On 8/26/2024 12:29 AM, Daniel Schultz wrote:
>> Hey Logan,
>>
>> my feedback is similar to Josua's.
>>
>> On 09.08.24 15:57, Logan Bristol wrote:
>>> External interfaces should be disabled at the SoC DTSI level, since
>>> the node is incomplete. Disable Ethernet switch and ports in SoC DTSI
>>> and enable them in the board DTS. If the board DTS includes a SoM DTSI
>>> that completes the node description, enable the Ethernet switch and
>>> ports
>>> in SoM DTSI.
>>>
>>> Reflect this change in SoM DTSIs by removing ethernet port disable.
>>>
>>> Signed-off-by: Logan Bristol <logan.bristol@utexas.edu>
>>> ---
>>> Changes since v1:
>>> - Enabled cpsw3g and cpsw_port1 in SoM DTSI instead of board DTS
>>> if board DTS included SoM DTSI
>>> ---
>>> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 3 +++
>>> arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 6 ++----
>>> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 3 +++
>>> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 3 +++
>>> arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 6 ++----
>>> arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 6 ++----
>>> 6 files changed, 15 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/
>>> boot/dts/ti/k3-am64-main.dtsi
>>> index f8370dd03350..69c5af58b727 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
>>> @@ -677,6 +677,7 @@ cpsw3g: ethernet@8000000 {
>>> assigned-clock-parents = <&k3_clks 13 9>;
>>> clock-names = "fck";
>>> power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
>>> + status = "disabled";
>>> dmas = <&main_pktdma 0xC500 15>,
>>> <&main_pktdma 0xC501 15>,
>>> @@ -701,6 +702,7 @@ cpsw_port1: port@1 {
>>> phys = <&phy_gmii_sel 1>;
>>> mac-address = [00 00 00 00 00 00];
>>> ti,syscon-efuse = <&main_conf 0x200>;
>>> + status = "disabled";
>>> };
>>> cpsw_port2: port@2 {
>>> @@ -709,6 +711,7 @@ cpsw_port2: port@2 {
>>> label = "port2";
>>> phys = <&phy_gmii_sel 2>;
>>> mac-address = [00 00 00 00 00 00];
>>> + status = "disabled";
>>> };
>>> };
>>> diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/
>>> arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
>>> index ea7c58fb67e2..6bece2fb4e95 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
>>> @@ -185,6 +185,7 @@ AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* (C19)
>>> EXTINTn.GPIO1_70 */
>>> &cpsw3g {
>>> pinctrl-names = "default";
>>> pinctrl-0 = <&cpsw_rgmii1_pins_default>;
>>> + status = "okay";
>>> };
>>> &cpsw3g_mdio {
>>> @@ -208,10 +209,7 @@ cpsw3g_phy1: ethernet-phy@1 {
>>> &cpsw_port1 {
>>> phy-mode = "rgmii-rxid";
>>> phy-handle = <&cpsw3g_phy1>;
>> The connected phy is located on the SOM and should be enabled by
>> default.
>>> -};
>>> -
>>> -&cpsw_port2 {
>>> - status = "disabled";
>>> + status = "okay";
>>> };
>>
>> This port is routed to the carrier-board. Please drop this node.
>
> I replied similarly to Josua's comments, but if cpsw_port1 is to be
> enabled and cpsw_port2 should be dropped from this DTSI, isn't that
> shown in this diff?
Ah, sorry. I did the same mistake :)
Acked-by: Daniel Schultz <d.schultz@phytec.de>
>
> Thank you,
> Logan Bristol
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2] arm64: dts: ti: k3-am64* Disable ethernet by default at SoC level
2024-08-09 13:57 [PATCH v2] arm64: dts: ti: k3-am64* Disable ethernet by default at SoC level Logan Bristol
2024-08-25 11:18 ` Josua Mayer
2024-08-26 5:29 ` Daniel Schultz
@ 2024-08-27 9:26 ` Matthias Schiffer
2024-08-28 18:41 ` Nishanth Menon
3 siblings, 0 replies; 9+ messages in thread
From: Matthias Schiffer @ 2024-08-27 9:26 UTC (permalink / raw)
To: Logan Bristol, Krzysztof Kozlowski, Conor Dooley,
Vignesh Raghavendra, Nishanth Menon
Cc: Josua Mayer, Matt McKee, Wadim Egorov, linux, devicetree,
linux-kernel, linux-arm-kernel
On Fri, 2024-08-09 at 08:57 -0500, Logan Bristol wrote:
>
> External interfaces should be disabled at the SoC DTSI level, since
> the node is incomplete. Disable Ethernet switch and ports in SoC DTSI
> and enable them in the board DTS. If the board DTS includes a SoM DTSI
> that completes the node description, enable the Ethernet switch and ports
> in SoM DTSI.
>
> Reflect this change in SoM DTSIs by removing ethernet port disable.
>
> Signed-off-by: Logan Bristol <logan.bristol@utexas.edu>
For the TQMa64xxL:
Acked-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
> ---
> Changes since v1:
> - Enabled cpsw3g and cpsw_port1 in SoM DTSI instead of board DTS
> if board DTS included SoM DTSI
> ---
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 3 +++
> arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi | 6 ++----
> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 3 +++
> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 3 +++
> arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 6 ++----
> arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts | 6 ++----
> 6 files changed, 15 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> index f8370dd03350..69c5af58b727 100644
> --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
> @@ -677,6 +677,7 @@ cpsw3g: ethernet@8000000 {
> assigned-clock-parents = <&k3_clks 13 9>;
> clock-names = "fck";
> power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
> + status = "disabled";
>
> dmas = <&main_pktdma 0xC500 15>,
> <&main_pktdma 0xC501 15>,
> @@ -701,6 +702,7 @@ cpsw_port1: port@1 {
> phys = <&phy_gmii_sel 1>;
> mac-address = [00 00 00 00 00 00];
> ti,syscon-efuse = <&main_conf 0x200>;
> + status = "disabled";
> };
>
> cpsw_port2: port@2 {
> @@ -709,6 +711,7 @@ cpsw_port2: port@2 {
> label = "port2";
> phys = <&phy_gmii_sel 2>;
> mac-address = [00 00 00 00 00 00];
> + status = "disabled";
> };
> };
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
> index ea7c58fb67e2..6bece2fb4e95 100644
> --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
> @@ -185,6 +185,7 @@ AM64X_IOPAD(0x0278, PIN_INPUT, 7) /* (C19) EXTINTn.GPIO1_70 */
> &cpsw3g {
> pinctrl-names = "default";
> pinctrl-0 = <&cpsw_rgmii1_pins_default>;
> + status = "okay";
> };
>
> &cpsw3g_mdio {
> @@ -208,10 +209,7 @@ cpsw3g_phy1: ethernet-phy@1 {
> &cpsw_port1 {
> phy-mode = "rgmii-rxid";
> phy-handle = <&cpsw3g_phy1>;
> -};
> -
> -&cpsw_port2 {
> - status = "disabled";
> + status = "okay";
> };
>
> &mailbox0_cluster2 {
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> index 6bb1ad2e56ec..82da21bd9aea 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> @@ -616,17 +616,20 @@ &cpsw3g {
> bootph-all;
> pinctrl-names = "default";
> pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
> + status = "okay";
> };
>
> &cpsw_port1 {
> bootph-all;
> phy-mode = "rgmii-rxid";
> phy-handle = <&cpsw3g_phy0>;
> + status = "okay";
> };
>
> &cpsw_port2 {
> phy-mode = "rgmii-rxid";
> phy-handle = <&cpsw3g_phy3>;
> + status = "okay";
> };
>
> &cpsw3g_mdio {
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> index 44ecbcf1c844..86369525259c 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> @@ -527,16 +527,19 @@ &usb0 {
> &cpsw3g {
> pinctrl-names = "default";
> pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
> + status = "okay";
> };
>
> &cpsw_port1 {
> phy-mode = "rgmii-rxid";
> phy-handle = <&cpsw3g_phy0>;
> + status = "okay";
> };
>
> &cpsw_port2 {
> phy-mode = "rgmii-rxid";
> phy-handle = <&cpsw3g_phy1>;
> + status = "okay";
> };
>
> &cpsw3g_mdio {
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
> index c19d0b8bbf0f..a5cec9a07510 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi
> @@ -177,6 +177,7 @@ vdd_mmc0: regulator-vdd-mmc0 {
> &cpsw3g {
> pinctrl-names = "default";
> pinctrl-0 = <&rgmii1_default_pins>;
> + status = "okay";
> };
>
> &cpsw3g_mdio {
> @@ -210,10 +211,7 @@ ethernet_phy0: ethernet-phy@0 {
> &cpsw_port1 {
> phy-mode = "rgmii-id";
> phy-handle = <ðernet_phy0>;
> -};
> -
> -&cpsw_port2 {
> - status = "disabled";
> + status = "okay";
> };
>
> &icssg1_mdio {
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
> index c40ad67cee01..8d7a0283c391 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
> @@ -119,15 +119,13 @@ reg_sd: regulator-sd {
> &cpsw3g {
> pinctrl-names = "default";
> pinctrl-0 = <&cpsw_pins>;
> + status = "okay";
> };
>
> &cpsw_port1 {
> phy-mode = "rgmii-rxid";
> phy-handle = <&cpsw3g_phy0>;
> -};
> -
> -&cpsw_port2 {
> - status = "disabled";
> + status = "okay";
> };
>
> &cpsw3g_mdio {
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
https://www.tq-group.com/
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v2] arm64: dts: ti: k3-am64* Disable ethernet by default at SoC level
2024-08-09 13:57 [PATCH v2] arm64: dts: ti: k3-am64* Disable ethernet by default at SoC level Logan Bristol
` (2 preceding siblings ...)
2024-08-27 9:26 ` Matthias Schiffer
@ 2024-08-28 18:41 ` Nishanth Menon
3 siblings, 0 replies; 9+ messages in thread
From: Nishanth Menon @ 2024-08-28 18:41 UTC (permalink / raw)
To: Krzysztof Kozlowski, Conor Dooley, Vignesh Raghavendra,
Logan Bristol
Cc: Nishanth Menon, Josua Mayer, Matt McKee, Wadim Egorov, linux,
devicetree, linux-kernel, linux-arm-kernel
Hi Logan Bristol,
On Fri, 09 Aug 2024 08:57:53 -0500, Logan Bristol wrote:
> External interfaces should be disabled at the SoC DTSI level, since
> the node is incomplete. Disable Ethernet switch and ports in SoC DTSI
> and enable them in the board DTS. If the board DTS includes a SoM DTSI
> that completes the node description, enable the Ethernet switch and ports
> in SoM DTSI.
>
> Reflect this change in SoM DTSIs by removing ethernet port disable.
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/1] arm64: dts: ti: k3-am64* Disable ethernet by default at SoC level
commit: fdf47b3a379b180403bd29b59e4159deff748e0b
I did check the change on phycore, it looks fine, and this patch seems to
have waited long enough.
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 9+ messages in thread