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X-CSE-ConnectionGUID: 1IxVERZORvisgyh249egGg== X-CSE-MsgGUID: ppgrXCKfSpe35wt4vgSFgw== X-IronPort-AV: E=McAfee;i="6700,10204,11405"; a="33998975" X-IronPort-AV: E=Sophos;i="6.15,216,1739865600"; d="scan'208";a="33998975" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2025 09:19:31 -0700 X-CSE-ConnectionGUID: HKeGjqQjS56WHzfCJFXFkA== X-CSE-MsgGUID: jSlVe6e9T7q6EjfwWGI6oQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,216,1739865600"; d="scan'208";a="131079341" Received: from lstrano-mobl6.amr.corp.intel.com (HELO [10.125.109.241]) ([10.125.109.241]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2025 09:19:31 -0700 Message-ID: <23e05939e7a19151d9b17d011e48a85d650b4e8a.camel@linux.intel.com> Subject: Re: [PATCH] sched: Skip useless sched_balance_running acquisition if load balance is not due From: Tim Chen To: Shrikanth Hegde , "Chen, Yu C" Cc: Vincent Guittot , Doug Nelson , Mohini Narkhede , linux-kernel@vger.kernel.org, Peter Zijlstra , Ingo Molnar Date: Wed, 16 Apr 2025 09:19:30 -0700 In-Reply-To: <5e191de4-f580-462d-8f93-707addafb9a2@linux.ibm.com> References: <20250416035823.1846307-1-tim.c.chen@linux.intel.com> <667f2076-fbcd-4da7-8e4b-a8190a673355@intel.com> <5e191de4-f580-462d-8f93-707addafb9a2@linux.ibm.com> Autocrypt: addr=tim.c.chen@linux.intel.com; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.4 (3.50.4-1.fc39) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2025-04-16 at 14:46 +0530, Shrikanth Hegde wrote: >=20 > On 4/16/25 11:58, Chen, Yu C wrote: > > Hi Shrikanth, > >=20 > > On 4/16/2025 1:30 PM, Shrikanth Hegde wrote: > > >=20 > > >=20 > > > On 4/16/25 09:28, Tim Chen wrote: > > > > At load balance time, balance of last level cache domains and > > > > above needs to be serialized. The scheduler checks the atomic var > > > > sched_balance_running first and then see if time is due for a load > > > > balance. This is an expensive operation as multiple CPUs can attemp= t > > > > sched_balance_running acquisition at the same time. > > > >=20 > > > > On a 2 socket Granite Rapid systems enabling sub-numa cluster and > > > > running OLTP workloads, 7.6% of cpu cycles are spent on cmpxchg of > > > > sched_balance_running.=C2=A0 Most of the time, a balance attempt is= aborted > > > > immediately after acquiring sched_balance_running as load balance t= ime > > > > is not due. > > > >=20 > > > > Instead, check balance due time first before acquiring > > > > sched_balance_running. This skips many useless acquisitions > > > > of sched_balance_running and knocks the 7.6% CPU overhead on > > > > sched_balance_domain() down to 0.05%.=C2=A0 Throughput of the OLTP = workload > > > > improved by 11%. > > > >=20 > > >=20 > > > Hi Tim. > > >=20 > > > Time check makes sense specially on large systems mainly due to=20 > > > NEWIDLE balance. >=20 > scratch the NEWLY_IDLE part from that comment. >=20 > > >=20 > >=20 > > Could you elaborate a little on this statement? There is no timeout=20 > > mechanism like periodic load balancer for the NEWLY_IDLE, right? >=20 > Yes. NEWLY_IDLE is very opportunistic. >=20 > >=20 > > > One more point to add, A lot of time, the CPU which acquired=20 > > > sched_balance_running, > > > need not end up doing the load balance, since it not the CPU meant to= =20 > > > do the load balance. > > >=20 > > > This thread. > > > https://lore.kernel.org/all/1e43e783-55e7-417f-=20 > > > a1a7-503229eb163a@linux.ibm.com/ > > >=20 > > >=20 > > > Best thing probably is to acquire it if this CPU has passed the time= =20 > > > check and as well it is > > > actually going to do load balance. > > >=20 > > >=20 > >=20 > > This is a good point, and we might only want to deal with periodic load > > balancer rather than NEWLY_IDLE balance. Because the latter is too=20 > > frequent and contention on the sched_balance_running might introduce > > high cache contention. > >=20 >=20 > But NEWLY_IDLE doesn't serialize using sched_balance_running and can=20 > endup consuming a lot of cycles. But if we serialize using=20 > sched_balance_running, it would definitely cause a lot contention as is. >=20 >=20 > The point was, before acquiring it, it would be better if this CPU is=20 > definite to do the load balance. Else there are chances to miss the=20 > actual load balance. >=20 You mean doing a should_we_balance() check? I think we should not even consider that if balance time is not due and this balance due check sh= ould come first. Do you have objection to switching the order of the time due check and seri= alization/sched_balance_running around as in this patch? Adding a change to see if this is the right balan= cing CPU could be an orthogonal change.=20 97% of CPU cycles in sched_balance_domains() are not spent doing useful loa= d balancing work, but simply in the acquisition of sched_balance_running in the OLTP workload= we tested. : : 104 static __always_inline int arch_atomic_cmpxchg(= atomic_t *v, int old, int new) : 105 { : 106 return arch_cmpxchg(&v->counter, old, new); 0.00 : ffffffff81138f8e: xor %eax,%eax 0.00 : ffffffff81138f90: mov $0x1,%ecx 0.00 : ffffffff81138f95: lock cmpxchg %ecx,0x2577d33(%rip) = # ffffffff836b0cd0 : 110 sched_balance_domains(): : 12146 if (atomic_cmpxchg_acquire(&sched_balance_runni= ng, 0, 1)) 97.01 : ffffffff81138f9d: test %eax,%eax 0.00 : ffffffff81138f9f: jne ffffffff81138fbb : 12150 if (time_after_eq(jiffies, sd->last_balance + i= nterval)) { 0.00 : ffffffff81138fa1: mov 0x16cfa18(%rip),%rax # f= fffffff828089c0 0.00 : ffffffff81138fa8: sub 0x48(%r14),%rax 0.00 : ffffffff81138fac: cmp %rdx,%rax 0.00 : ffffffff81138faf: jns ffffffff8113900f : 12155 raw_atomic_set_release(): So trying to skip this unnecessary acquisition and consider load balancing = only when time is due. Tim >=20 > > thanks, > > Chenyu > >=20 > > > > Signed-off-by: Tim Chen > > > > Reported-by: Mohini Narkhede > > > > Tested-by: Mohini Narkhede > > > > --- > > > > =C2=A0 kernel/sched/fair.c | 16 ++++++++-------- > > > > =C2=A0 1 file changed, 8 insertions(+), 8 deletions(-) > > > >=20 > > > > diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c > > > > index e43993a4e580..5e5f7a770b2f 100644 > > > > --- a/kernel/sched/fair.c > > > > +++ b/kernel/sched/fair.c > > > > @@ -12220,13 +12220,13 @@ static void sched_balance_domains(struct = rq=20 > > > > *rq, enum cpu_idle_type idle) > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 interval =3D= get_sd_balance_interval(sd, busy); > > > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 need_serialize =3D sd->= flags & SD_SERIALIZE; > > > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (need_serialize) { > > > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= if (atomic_cmpxchg_acquire(&sched_balance_running, 0, 1)) > > > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 goto out; > > > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } > > > > - > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (time_aft= er_eq(jiffies, sd->last_balance + interval)) { > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= need_serialize =3D sd->flags & SD_SERIALIZE; > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= if (need_serialize) { > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 if (atomic_cmpxchg_acquire(&sched_balance_running,= =20 > > > > 0, 1)) > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 goto out; > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= } > > > > + > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 if (sched_balance_rq(cpu, rq, sd, idle,=20 > > > > &continue_balancing)) { > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 /* > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * The LBF_DST_PINNED logic could= have changed > > > > @@ -12238,9 +12238,9 @@ static void sched_balance_domains(struct rq= =20 > > > > *rq, enum cpu_idle_type idle) > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 } > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 sd->last_balance =3D jiffies; > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 interval =3D get_sd_balance_interval(sd, busy); > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= if (need_serialize) > > > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 atomic_set_release(&sched_balance_running, 0); > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } > > > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (need_serialize) > > > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= atomic_set_release(&sched_balance_running, 0); > > > > =C2=A0 out: > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (time_aft= er(next_balance, sd->last_balance + interval)) { > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 next_balance =3D sd->last_balance + interval; > > >=20 >=20 >=20