From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A521C47404 for ; Mon, 7 Oct 2019 13:26:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4A63620679 for ; Mon, 7 Oct 2019 13:26:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728238AbfJGN0P (ORCPT ); Mon, 7 Oct 2019 09:26:15 -0400 Received: from gloria.sntech.de ([185.11.138.130]:57050 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727923AbfJGN0N (ORCPT ); Mon, 7 Oct 2019 09:26:13 -0400 Received: from ip5f5a6266.dynamic.kabel-deutschland.de ([95.90.98.102] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1iHT1c-0003CU-B8; Mon, 07 Oct 2019 15:26:08 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: srinivas.kandagatla@linaro.org, robh+dt@kernel.org Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, christoph.muellner@theobroma-systems.com Subject: Re: [PATCH 1/2] dt-bindings: nvmem: add binding for Rockchip OTP controller Date: Mon, 07 Oct 2019 15:26:07 +0200 Message-ID: <2431603.e1tpym8sWD@diego> In-Reply-To: <20190925184957.14338-1-heiko@sntech.de> References: <20190925184957.14338-1-heiko@sntech.de> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Rob, Am Mittwoch, 25. September 2019, 20:49:56 CEST schrieb Heiko Stuebner: > Newer Rockchip SoCs use a different IP for accessing special one- > time-programmable memory, so add a binding for these controllers. > > Signed-off-by: Heiko Stuebner Srinivas seems to wait for an Ack on the DT-Patch - see comment on patch2. As this all looks pretty standard, any objections to the binding? Thanks Heiko > --- > .../bindings/nvmem/rockchip-otp.txt | 25 +++++++++++++++++++ > 1 file changed, 25 insertions(+) > create mode 100644 Documentation/devicetree/bindings/nvmem/rockchip-otp.txt > > diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt b/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt > new file mode 100644 > index 000000000000..40f649f7c2e5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/nvmem/rockchip-otp.txt > @@ -0,0 +1,25 @@ > +Rockchip internal OTP (One Time Programmable) memory device tree bindings > + > +Required properties: > +- compatible: Should be one of the following. > + - "rockchip,px30-otp" - for PX30 SoCs. > + - "rockchip,rk3308-otp" - for RK3308 SoCs. > +- reg: Should contain the registers location and size > +- clocks: Must contain an entry for each entry in clock-names. > +- clock-names: Should be "otp", "apb_pclk" and "phy". > +- resets: Must contain an entry for each entry in reset-names. > + See ../../reset/reset.txt for details. > +- reset-names: Should be "phy". > + > +See nvmem.txt for more information. > + > +Example: > + otp: otp@ff290000 { > + compatible = "rockchip,px30-otp"; > + reg = <0x0 0xff290000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <1>; > + clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, > + <&cru PCLK_OTP_PHY>; > + clock-names = "otp", "apb_pclk", "phy"; > + }; >