From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 01A332236E0 for ; Mon, 1 Jun 2026 09:52:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780307580; cv=none; b=VTKVS1jJZ/N21zYZ/2wJKHrtbMxHFY0gcwwuBvZYsBO6BjdSKB0i19l26Ye+5lCB1r9O2KLJuWkaNLHtqNvSFzoJN7BjKyc9HytzwNdAw2DRopOd8KsEqhiKTqRx8HaxjaXIVYQriuDUr4GyLSv+QVg/xbJ2c+9NO8X0iUpT3Ms= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780307580; c=relaxed/simple; bh=LFDJQmDrINHw4OwHKny0l67PJC4qq1iRplJcbH2pqlw=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=XTQN9G0waEV+aUcwlAyTMiDYWaRPR9yohGMYIz9N+DEWmZ3Zal26wwYlDzxuSvDrxz0rwR3GDt08U69aCj4r8W1ulw5N0Bysctd5iXOBgfpUg8C4mB78VseUEjx33gDp9UcHHXV/qdJRwHJFdMxAlC+a5qo0rZ+F6snxIlIp8QA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=gbnsSzK1; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="gbnsSzK1" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D03631682; Mon, 1 Jun 2026 02:52:42 -0700 (PDT) Received: from [10.1.38.31] (Suzukis-MBP.cambridge.arm.com [10.1.38.31]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AC22C3F905; Mon, 1 Jun 2026 02:52:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1780307567; bh=LFDJQmDrINHw4OwHKny0l67PJC4qq1iRplJcbH2pqlw=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=gbnsSzK1VxRgugA3da6ax6XRunC1jQ0BRaH0MPkaPDmH9hpAljqekOdMutsEkBjjD SzR2E3Cl5Eaxz0CigYZBlQIJH0WqtpBvQ0M2HiqMYeibDHg24rM+PZH9CGa3t7Sxxv ytg8zZGJMIara9iGNvlkZnpcNWyjAS5GWfxxsUxE= Message-ID: <24427ef2-8d32-4c29-b652-bf1019e04f40@arm.com> Date: Mon, 1 Jun 2026 10:52:45 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 02/13] coresight: etm4x: fix underflow for nrseqstate Content-Language: en-GB To: Yeoreum Yun , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com References: <20260519154812.254884-1-yeoreum.yun@arm.com> <20260519154812.254884-3-yeoreum.yun@arm.com> From: Suzuki K Poulose In-Reply-To: <20260519154812.254884-3-yeoreum.yun@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 19/05/2026 16:48, Yeoreum Yun wrote: > TCRSEQEVR is implemented only when TCRIDR5.NUMSEQSTATE is 0b100, > in which case n ranges from 0 to 2; otherwise, TCRIDR5.NUMSEQSTATE is 0b000. > > Therefore, drvdata->nrseqstate should be checked before entering the loop. s/TCR/TRC/g ^^^ and every other patch in the series. Seem like you have been playing with the MMU code ;-) > > Link: https://developer.arm.com/documentation/ihi0064/latest/ [0] > Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver") > Reviewed-by: Leo Yan > Signed-off-by: Yeoreum Yun > --- > .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++-------- > .../coresight/coresight-etm4x-sysfs.c | 2 ++ > 2 files changed, 12 insertions(+), 8 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index 1e3b0344dc00..94b9385e964a 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -542,9 +542,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR); > if (drvdata->nr_pe_cmp) > etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); > - for (i = 0; i < drvdata->nrseqstate - 1; i++) > - etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); > + > if (drvdata->nrseqstate) { > + for (i = 0; i < drvdata->nrseqstate - 1; i++) > + etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); Looking at this again, I think we are contemplating two different values from a single variable (blame the architecture). Instead, we should: 1. Disconnect number of TRCSEQEVRn from drvdata->nrseqstate, and add nr_seq_ctrls to drvdata and initialise this at probe. for (i = 0; i < drvdata->nr_seq_ctrls; i++) Suzuki > + > etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); > } > @@ -1896,10 +1898,10 @@ static int etm4_cpu_save(struct coresight_device *csdev) > if (drvdata->nr_pe_cmp) > state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR); > > - for (i = 0; i < drvdata->nrseqstate - 1; i++) > - state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); > - > if (drvdata->nrseqstate) { > + for (i = 0; i < drvdata->nrseqstate - 1; i++) > + state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); > + > state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); > state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); > } > @@ -2009,10 +2011,10 @@ static void etm4_cpu_restore(struct coresight_device *csdev) > if (drvdata->nr_pe_cmp) > etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR); > > - for (i = 0; i < drvdata->nrseqstate - 1; i++) > - etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); > - > if (drvdata->nrseqstate) { > + for (i = 0; i < drvdata->nrseqstate - 1; i++) > + etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); > + > etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); > etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); > } > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > index e9eeea6240d5..0e1ad175aa1e 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > @@ -1395,6 +1395,8 @@ static ssize_t seq_idx_store(struct device *dev, > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > struct etmv4_config *config = &drvdata->config; > > + if (!drvdata->nrseqstate) > + return -ENOTSUPP; > if (kstrtoul(buf, 16, &val)) > return -EINVAL; > if (val >= drvdata->nrseqstate - 1)