Re: [PATCH v5 11/14] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt

Rob Herring
2022-02-04T22:33:47Z

On Fri, Jan 21, 2022 at 05:36:15PM +0100, Heiko Stuebner wrote:
> From: Wei Fu <wefu@redhat.com>
>
> Previous patch has added svpbmt in arch/riscv and add "riscv,svpmbt"
> in the DT mmu node. Update dt-bindings related property here.
>
> Signed-off-by: Wei Fu <wefu@redhat.com>
> Co-developed-by: Guo Ren <guoren@kernel.org>
> Signed-off-by: Guo Ren <guoren@kernel.org>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> Cc: Anup Patel <anup@brainfault.org>
> Cc: Palmer Dabbelt <palmer@dabbelt.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index aa5fb64d57eb..3ad2593f1400 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -63,6 +63,16 @@ properties:
> - riscv,sv48
> - riscv,none
>
> + mmu:

riscv,mmu

> + description:
> + Describes the CPU's MMU Standard Extensions support.
> + These values originate from the RISC-V Privileged
> + Specification document, available from
> + https://riscv.org/specifications/
> + $ref: '/schemas/types.yaml#/definitions/string'
> + enum:
> + - riscv,svpbmt

Are there per vendor MMU extensions? If not, drop the 'riscv,' part.

> +
> riscv,isa:
> description:
> Identifies the specific RISC-V instruction set architecture
> --
> 2.30.2
>
>