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Convert the value from nanoseconds to a hardware > encoded 3-bit value that is equal to log2(ns/1000) + 1. If the property > is absent or greater than 7 (the maximum latency value supported), then > default to 7. > > Signed-off-by: Manikanta Maddireddy > --- > V2: Fixed commit message as per review comments. > > drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c > index 9dcfa194050e..c9716d614451 100644 > --- a/drivers/pci/controller/dwc/pcie-tegra194.c > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c > @@ -18,6 +18,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -272,6 +273,7 @@ struct tegra_pcie_dw { > u32 aspm_cmrt; > u32 aspm_pwr_on_t; > u32 aspm_l0s_enter_lat; > + u32 aspm_l1_enter_lat; > > struct regulator *pex_ctl_supply; > struct regulator *slot_ctl_3v3; > @@ -715,6 +717,8 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) > val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); > val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK; > val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); > + val &= ~PORT_AFR_L1_ENTRANCE_LAT_MASK; > + val |= (pcie->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT); > val |= PORT_AFR_ENTER_ASPM; > dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); > } > @@ -1115,6 +1119,7 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) > { > struct platform_device *pdev = to_platform_device(pcie->dev); > struct device_node *np = pcie->dev->of_node; > + u32 val; > int ret; > > pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); > @@ -1141,6 +1146,15 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) > dev_info(pcie->dev, > "Failed to read ASPM L0s Entrance latency: %d\n", ret); > > + /* Default to max latency of 7. */ > + pcie->aspm_l1_enter_lat = 7; > + ret = of_property_read_u32(np, "aspm-l1-entry-delay-ns", &val); > + if (!ret) { > + u32 us = max(val / 1000, 1U); > + > + pcie->aspm_l1_enter_lat = min(ilog2(us) + 1, 7); > + } > + > ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes); > if (ret < 0) { > dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret); Reviewed-by: Jon Hunter Thanks! Jon -- nvpublic