From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5180331E85E; Thu, 7 May 2026 08:15:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778141753; cv=none; b=s0wyxlhviHwYRmCCroniNqmzsNdXSKCuVwt2sKmhOWQwcSMTio/vLaPg/HnqBkiDvHeTiKb3shXjmShUWMU93V6rOd7UYO3xB2Ry3+CTVxvrbYtz4RDYBAc2ye6Lb+yOA0OptvSJ09V6Hk3CTTqxFVkXTgxCQmwcYXOh5UNSCMQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778141753; c=relaxed/simple; bh=mMLd+FkExonZSdmM2rLtjk2Xc3hYAUR64eyWBI0/hoU=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=NJFVv+hhXA1JMnP8qpfgfggTrDApNqmj65tGdWvI06+W/HFiXNbgRBS8T3FVx6+dn1rct1WVEHnl0N8cYmAvuOthD6f47O/5sNjS+mTleXrQ26EmyJbuaz1ciWMc9pQMW6bMxTk9uzqlx3UOoA4j88W1iAflBDeETTywHNF4ufY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Ojbc7Snh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Ojbc7Snh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C12A1C2BCB8; Thu, 7 May 2026 08:15:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778141753; bh=mMLd+FkExonZSdmM2rLtjk2Xc3hYAUR64eyWBI0/hoU=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Ojbc7Snh+cqQDEhbNxEFQgAx9OXSAYI4D25DRczcAsclAIx9RDDYAwaPM/ylK5JCB 3nmr0WbN/zbIPnj0PEcHhwf+uOF04F5Iqlleh6SgN2HJLbS3sNt4eHN6xrmVFwmwHc syjCEgFzWpG4aLro+ZgpzpY5kVpK+Ur2MXIEhuzoyZNjtzWZwo7+SEZGP+VZBrkzHp QF4drzw/a/9/wV4Y5cY1Z9g7YZt09NgAQfGcVtIuobELmsl2bMEZeSp4Qu/JDB2wzu PJgPTrwdplCorhXFYhoyRSx6FITb/ionb0nSnn839/Nxwkmm5jvSYiN05EimpLdLbI HJdmm6bXICLTg== Message-ID: <26191034-ad27-4559-a845-14841c075a4c@kernel.org> Date: Thu, 7 May 2026 09:15:48 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 5/6] clk: qcom: camcc-x1p42100: Add support for camera clock controller To: Jagadeesh Kona , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Jagadeesh Kona , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio References: <20260507-purwa-videocc-camcc-v5-0-fc3af4130282@oss.qualcomm.com> <20260507-purwa-videocc-camcc-v5-5-fc3af4130282@oss.qualcomm.com> From: Bryan O'Donoghue Content-Language: en-US Autocrypt: addr=bod@kernel.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 07/05/2026 06:38, Jagadeesh Kona wrote: > +static const struct alpha_pll_config cam_cc_pll1_config = { > + .l = 0x25, > + .alpha = 0xeaaa, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00182261, > + .config_ctl_hi1_val = 0x82aa299c, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000003, > + .test_ctl_hi1_val = 0x00009000, > + .test_ctl_hi2_val = 0x00000034, > + .user_ctl_val = 0x00000400, > + .user_ctl_hi_val = 0x00000005, > +}; Since its a script that generates most of this code, can't you teach it to enumerate these magic numbers with defines and bit-fields ? I'm not sure if I got an answer to that question on the last iteration of this patch but, asking again now. --- bod