From: "CK Hu (胡俊光)" <ck.hu@mediatek.com>
To: "robh@kernel.org" <robh@kernel.org>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"Paul-pl Chen (陳柏霖)" <Paul-pl.Chen@mediatek.com>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>,
"chunkuang.hu@kernel.org" <chunkuang.hu@kernel.org>
Cc: "Sunny Shen (沈姍姍)" <Sunny.Shen@mediatek.com>,
"Sirius Wang (王皓昱)" <Sirius.Wang@mediatek.com>,
"Nancy Lin (林欣螢)" <Nancy.Lin@mediatek.com>,
"Xiandong Wang (王先冬)" <Xiandong.Wang@mediatek.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
"linux-mediatek@lists.infradead.org"
<linux-mediatek@lists.infradead.org>,
"Jason-JH Lin (林睿祥)" <Jason-JH.Lin@mediatek.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"fshao@chromium.org" <fshao@chromium.org>,
"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
"Singo Chang (張興國)" <Singo.Chang@mediatek.com>,
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"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
"treapking@chromium.org" <treapking@chromium.org>
Subject: Re: [PATCH v4 12/19] drm/mediatek: Export OVL formats definitions and format conversion API
Date: Wed, 10 Sep 2025 07:19:00 +0000 [thread overview]
Message-ID: <2621389158b89dfa3894f0f4f2ff80019077f729.camel@mediatek.com> (raw)
In-Reply-To: <20250828080855.3502514-13-paul-pl.chen@mediatek.com>
On Thu, 2025-08-28 at 16:07 +0800, Paul Chen wrote:
> From: Nancy Lin <nancy.lin@mediatek.com>
>
> In upcoming SoCs, the OVL component will be divided into multiple
> smaller hardware units to enhance flexibility. To facilitate this
> transition, the OVL format definitions and format conversion API
> should be exported for reuse across these units.
>
> Signed-off-by: Nancy Lin <nancy.lin@mediatek.com>
> Signed-off-by: Paul-pl Chen <paul-pl.chen@mediatek.com>
> ---
[snip]
>
> +bool mtk_ovl_is_10bit_rgb(unsigned int fmt)
You add mtk_ovl_is_10bit_rgb() here, so you should remove is_10bit_rgb().
> +{
> + switch (fmt) {
> + case DRM_FORMAT_XRGB2101010:
> + case DRM_FORMAT_ARGB2101010:
> + case DRM_FORMAT_RGBX1010102:
> + case DRM_FORMAT_RGBA1010102:
> + case DRM_FORMAT_XBGR2101010:
> + case DRM_FORMAT_ABGR2101010:
> + case DRM_FORMAT_BGRX1010102:
> + case DRM_FORMAT_BGRA1010102:
> + return true;
> + }
> + return false;
> +}
> +
[snip]
> static void mtk_ovl_afbc_layer_config(struct mtk_disp_ovl *ovl,
> @@ -511,7 +550,15 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
> return;
> }
>
> - con = mtk_ovl_fmt_convert(ovl, state);
> + if (ovl->data->blend_modes & BIT(DRM_MODE_BLEND_PREMULTI))
> + con = mtk_ovl_fmt_convert(fmt, blend_mode,
> + ovl->data->fmt_rgb565_is_0, true, 12,
Why color_convert is true for all fmt?
In original code, only YUV format would do color convert.
> + OVL_CON_CLRFMT_MAN, OVL_CON_BYTE_SWAP, OVL_CON_RGB_SWAP);
> + else
> + con = mtk_ovl_fmt_convert(fmt, DRM_MODE_BLEND_COVERAGE,
> + ovl->data->fmt_rgb565_is_0, true, 12,
Symbolize 12. Maybe
#define OVL_CON_CLRFMT_SHIFT 12
> + OVL_CON_CLRFMT_MAN, OVL_CON_BYTE_SWAP, OVL_CON_RGB_SWAP);
> +
> if (state->base.fb) {
> con |= state->base.alpha & OVL_CON_ALPHA;
>
> @@ -668,7 +715,7 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
> .layer_nr = 4,
> .fmt_rgb565_is_0 = false,
> .formats = mt8173_ovl_formats,
> - .num_formats = ARRAY_SIZE(mt8173_ovl_formats),
> + .num_formats = mt8173_ovl_formats_len,
> };
>
[snip]
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
> new file mode 100644
> index 000000000000..4f446d2e0712
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2025 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_DISP_OVL_H__
> +#define __MTK_DISP_OVL_H__
> +
> +#include <drm/drm_fourcc.h>
> +
> +extern const u32 mt8173_ovl_formats[];
No other file need mt8173_ovl_formats[], so do not export it.
> +extern const size_t mt8173_ovl_formats_len;
> +extern const u32 mt8195_ovl_formats[];
> +extern const size_t mt8195_ovl_formats_len;
> +
> +bool mtk_ovl_is_10bit_rgb(unsigned int fmt);
> +unsigned int mtk_ovl_fmt_convert(unsigned int fmt, unsigned int blend_mode,
> + bool fmt_rgb565_is_0, bool color_convert,
> + u8 clrfmt_shift, u32 clrfmt_man, u32 byte_swap, u32 rgb_swap);
> +
> +#endif
next prev parent reply other threads:[~2025-09-10 7:34 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-28 8:06 [PATCH v4 00/19] Add MediaTek SoC DRM support for MT8196 Paul Chen
2025-08-28 8:06 ` [PATCH v4 01/19] dt-bindings: arm: mediatek: mmsys: add compatible " Paul Chen
2025-08-28 8:06 ` [PATCH v4 02/19] dt-bindings: soc: mediatek: add mutex yaml " Paul Chen
2025-08-28 8:06 ` [PATCH v4 03/19] dt-bindings: display: mediatek: add EXDMA " Paul Chen
2025-08-28 13:30 ` Rob Herring (Arm)
2025-08-29 6:35 ` Krzysztof Kozlowski
2025-08-29 6:48 ` Krzysztof Kozlowski
2025-08-29 11:10 ` Paul-pl Chen (陳柏霖)
2025-09-18 7:01 ` CK Hu (胡俊光)
2025-09-18 11:25 ` AngeloGioacchino Del Regno
2025-08-28 8:06 ` [PATCH v4 04/19] dt-bindings: display: mediatek: add BLENDER " Paul Chen
2025-08-28 8:07 ` [PATCH v4 05/19] dt-bindings: display: mediatek: add OUTPROC " Paul Chen
2025-08-29 6:49 ` Krzysztof Kozlowski
2025-08-28 8:07 ` [PATCH v4 06/19] soc: mediatek: Add runtime PM and top clocks and async controls for MMSYS Paul Chen
2025-09-16 2:01 ` CK Hu (胡俊光)
2025-09-16 3:03 ` CK Hu (胡俊光)
2025-12-17 7:57 ` Paul-pl Chen (陳柏霖)
2025-08-28 8:07 ` [PATCH v4 07/19] soc: mediatek: add mmsys support for MT8196 Paul Chen
2025-08-28 8:07 ` [PATCH v4 08/19] soc: mediatek: mutex: Reused the switch case for SOF ID Paul Chen
2025-09-16 6:00 ` CK Hu (胡俊光)
2025-08-28 8:07 ` [PATCH v4 09/19] soc: mediatek: mutex: refactor SOF settings for output components Paul Chen
2025-09-17 1:16 ` CK Hu (胡俊光)
2025-08-28 8:07 ` [PATCH v4 10/19] soc: mediatek: mutex: add mutex support for MT8196 Paul Chen
2025-08-28 8:07 ` [PATCH v4 11/19] drm/mediatek: Rename OVL format naming Paul Chen
2025-09-01 2:45 ` CK Hu (胡俊光)
2025-08-28 8:07 ` [PATCH v4 12/19] drm/mediatek: Export OVL formats definitions and format conversion API Paul Chen
2025-09-10 7:19 ` CK Hu (胡俊光) [this message]
2025-08-28 8:07 ` [PATCH v4 13/19] drm/mediatek: Export OVL Blend function Paul Chen
2025-09-10 9:18 ` CK Hu (胡俊光)
2025-12-19 17:00 ` Paul-pl Chen (陳柏霖)
2025-08-28 8:07 ` [PATCH v4 14/19] drm/mediatek: add EXDMA support for MT8196 Paul Chen
2025-09-11 11:24 ` CK Hu (胡俊光)
2025-08-28 8:07 ` [PATCH v4 15/19] drm/mediatek: add BLENDER " Paul Chen
2025-09-12 2:27 ` CK Hu (胡俊光)
2025-12-19 17:03 ` Paul-pl Chen (陳柏霖)
2025-08-28 8:07 ` [PATCH v4 16/19] drm/mediatek: add OUTPROC " Paul Chen
2025-09-15 1:33 ` CK Hu (胡俊光)
2025-08-28 8:07 ` [PATCH v4 17/19] drm/mediatek: add ovlsys_adaptor " Paul Chen
2025-09-10 12:25 ` AngeloGioacchino Del Regno
2025-09-15 9:28 ` CK Hu (胡俊光)
2025-08-28 8:07 ` [PATCH v4 18/19] drm/mediatek: Add support for multiple mmsys in the one mediatek-drm driver Paul Chen
2025-09-10 12:24 ` AngeloGioacchino Del Regno
2025-09-16 6:12 ` Paul-pl Chen (陳柏霖)
2025-09-16 3:11 ` CK Hu (胡俊光)
2025-08-28 8:07 ` [PATCH v4 19/19] drm/mediatek: Add support for MT8196 multiple mmsys Paul Chen
2025-09-16 1:47 ` CK Hu (胡俊光)
2025-08-29 6:32 ` [PATCH v4 00/19] Add MediaTek SoC DRM support for MT8196 Krzysztof Kozlowski
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